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? freescale semiconductor, inc., 2009. all rights reserved. freescale semiconductor technical data 1overview this section provides a high- level overview of mpc8548e features. figure 1 shows the major functional units within the mpc8548e. although this document is written from the perspective of the mpc8548e, most of the material applies to the other family members?mpc8547e, mpc8545e, and mpc8543e?as well. when specific differences occur, such as pinout differences and processor frequency ranges, they will be identified as such. for specific pvr and svr numbers, refer to the mpc8548e powerquicc? iii integrated processor family reference manual. contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . 10 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 4. input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. ddr and ddr2 sdram . . . . . . . . . . . . . . . . . . . . . 19 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. enhanced three-speed ethernet (etsec) . . . . . . . . 26 9. ethernet management interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11. programmable interrupt controller . . . . . . . . . . . . . 51 12. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14. pci/pci-x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15. high-speed serial interfaces (hssi) . . . . . . . . . . . . 60 16. pci express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 17. serial rapidio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18. package description . . . . . . . . . . . . . . . . . . . . . . . . . 86 19. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 20. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 21. system design information . . . . . . . . . . . . . . . . . . 127 22. ordering information . . . . . . . . . . . . . . . . . . . . . . . 136 23. document revision history . . . . . . . . . . . . . . . . . . 139 mpc8548e powerquicc? iii integrated processor hardware specifications document number: mpc8548eec rev. 5, 10/2009
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 2 freescale semiconductor overview figure 1. mpc8548e block diagram 1.1 key features the following list provides an overview of the mpc8548e feature set: ? high-performance 32-bit core built on power architecture? technology. ? 32-kbyte l1 instruction cache and 32-kbyte l1 data cache with parity protection. caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. ? signal-processing engine (spe) apu (auxilia ry processing unit). provides an extensive instruction set for vector (64-bit) integer and fractional operations. these instructions use both the upper and lower words of the 64-bit gprs as they are defined by the spe apu. ? double-precision floating-point apu. provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit gprs. ? 36-bit real addressing ? embedded vector and scalar single-precision fl oating-point apus. provide an instruction set for single-precision (32-bit) floating-point instructions. ? memory management unit (mmu). especially designed for embedded applications. supports 4-kbyte?4-gbyte page sizes. ? enhanced hardware and software debug support core complex x8 pci express 4x rapidio 66 mhz pci 32-bit 10/100/1gb mii, gmii, tbi, rtbi, rgmii, serial irqs sdram ddr flash sdram gpio bus i 2 c i 2 c controller etsec 32-bit pci bus interface (if 64-bit not used) e500 coherency module ddr/ddr2/ memory controller local bus controller programmable interrupt controller (pic) duart e500 core 512-kbyte l2 cache/ sram 32-bit pci/ 64-bit pci/pci-x bus interface 32-kbyte l1 instruction cache 32-kbyte l1 data cache ocean switch fabric serial rapidio? or pci express 4-channel dma controller 133 mhz pci/pci-x i 2 c i 2 c controller rmii 10/100/1gb mii, gmii, tbi, rtbi, rgmii, etsec rmii 10/100/1gb mii, gmii, tbi, rtbi, rgmii, etsec rmii 10/100/1gb rtbi, rgmii, etsec security engine xor engine rmii
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 3 overview ? performance monitor facility that is similar to , but separate from, the mpc8548e performance monitor the e500 defines features that are not implemented on th is device. it also generally defines some features that this device implements more specifically. an understanding of these differences can be critical to ensure proper operations. ? 512-kbyte l2 cache/sram ? flexible configuration. ? full ecc support on 64-bit boundary in both cache and sram modes ? cache mode supports instruction caching, data caching, or both. ? external masters can force data to be allo cated into the cache through programmed memory ranges or special transaction types (stashing). ? 1, 2, or 4 ways can be configured for stashing only. ? eight-way set-associative cache organization (32-byte cache lines) ? supports locking entire cache or selected lines. individual line locks are set and cleared through book e instructions or by externally mastered transactions. ? global locking and flash clearing done thr ough writes to l2 configuration registers ? instruction and data locks can be flash cleared separately. ? sram features include the following: ? i/o devices access sram regions by marking transactions as snoopable (global). ? regions can reside at any ali gned location in the memory map. ? byte-accessible ecc is protected using read-modify-write transaction accesses for smaller-than-cache-line accesses. ? address translation and mapping unit (atmu) ? eight local access windows define mapping within local 36-bit address space. ? inbound and outbound atmus map to larger external address spaces. ? three inbound windows plus a configuration window on pci/pci-x and pci express ? four inbound windows plus a default window on rapidio? ? four outbound windows plus default translation for pci/pci-x and pci express ? eight outbound windows plus default transla tion for rapidio with segmentation and sub-segmentation support ? ddr/ddr2 memory controller ? programmable timing supporting ddr and ddr2 sdram ? 64-bit data interface ? four banks of memory supported, each up to 4 gbytes, to a maximum of 16 gbytes ? dram chip configurations from 64 mbits to 4 gbits with x8/x16 data ports ? full ecc support ? page mode support ? up to 16 simultaneous open pages for ddr
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 4 freescale semiconductor overview ? up to 32 simultaneous open pages for ddr2 ? contiguous or discontiguous memory mapping ? read-modify-write support for rapidio atomic increment, decrement, set, and clear transactions ? sleep mode support for self-refresh sdram ? on-die termination support when using ddr2 ? supports auto refreshing ? on-the-fly power management using cke signal ? registered dimm support ? fast memory access via jtag port ? 2.5-v sstl_2 compatible i/o (1.8-v sstl_1.8 for ddr2) ? support for battery-backed main memory ? programmable interrupt controller (pic) ? programming model is compliant with the openpic architecture. ? supports 16 programmable interrupt a nd processor task priority levels ? supports 12 discrete external interrupts ? supports 4 message interrupts with 32-bit messages ? supports connection of an external interr upt controller such as the 8259 programmable interrupt controller ? four global high resolution timers/count ers that can generate interrupts ? supports a variety of other internal interrupt sources ? supports fully nested interrupt delivery ? interrupts can be routed to external pin for external processing. ? interrupts can be routed to the e500 core ?s standard or critical interrupt inputs. ? interrupt summary registers allow fast identification of interrupt source. ? integrated security engine (sec) optimized to pr ocess all the algorithms associated with ipsec, ike, wtls/wap, ssl/tls, and 3gpp ? four crypto-channels, each supporting multi-command descriptor chains ? dynamic assignment of crypto-execution units via an integrated controller ? buffer size of 256 bytes for each execution unit, with flow control for large data sizes ? pkeu?public key execution unit ? rsa and diffie-hellman; programmable field size up to 2048 bits ? elliptic curve cryptography with f 2 m and f(p) modes and programmable field size up to 511 bits ? deu?data encryption standard execution unit ? des, 3des ? two key (k1, k2) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 5 overview ? aesu?advanced encryption standard unit ? implements the rijndael symmetric key cipher ? ecb, cbc, ctr, and ccm modes ? 128-, 192-, and 256-bit key lengths ? afeu?arc four execution unit ? implements a stream cipher compatible with the rc4 algorithm ? 40- to 128-bit programmable key ? mdeu?message digest execution unit ? sha with 160- or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? keu?kasumi execution unit ? implements f8 algorithm for encryption and f9 algorithm for integrity checking ? also supports a5/3 and gea-3 algorithms ? rng?random number generator ? xor engine for parity checking in raid storage applications ? dual i 2 c controllers ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? boot sequencer ? optionally loads configuration data from serial rom at reset via the i 2 c interface ? can be used to initialize configuration registers and/or memory ? supports extended i 2 c addressing mode ? data integrity checked with preamble signature and crc ? duart ? two 4-wire interfaces (sin, sout, rts , cts ) ? programming model compatible with the original 16450 uart and the pc16550d ? local bus controller (lbc) ? multiplexed 32-bit address and data bus operating at up to 133 mhz ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? the 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. ? three protocol engines availa ble on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user programmable machines (upms)
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 6 freescale semiconductor overview ? dedicated single data rate sdram controller ? parity support ? default boot rom chip select with configurable bus width (8, 16, or 32 bits) ? four enhanced three-speed ethernet controllers (etsecs) ? three-speed support (10/100/1000 mbps) ? four controllers designed to comply with ieee std. 802.3?, 802.3u?, 802.3x?, 802.3z?, 802.3ac?, and 802.3ab? ? support for various ethernet physical interfaces: ? 1000 mbps full-duplex ieee 802.3 gmii, ieee 802.3z tbi, rtbi, and rgmii ? 10/100 mbps full and half-duplex ieee 802.3 mii, ieee 802.3 rgmii, and rmii ? flexible configuration for multiple phy interface configurations. see section 8.1, ?enhanced three-speed ethernet controller (etsec) (10/100/1gb mbps)?gmii/mii/tbi/rgmii/rtbi/rmii electrical characteristics,? for more information. ? tcp/ip acceleration and qos features available ? ip v4 and ip v6 header recognition on receive ? ip v4 header checksum verification and generation ? tcp and udp checksum verification and generation ? per-packet configurable acceleration ? recognition of vlan, stacked (queue in queue) vlan, ieee std 802.2?, pppoe session, mpls stacks, and esp/ah ip-security headers ? supported in all fifo modes ? quality of service support: ? transmission from up to eight physical queues ? reception to up to eight physical queues ? full- and half-duplex ethernet support (1000 mbps supports only full duplex): ? ieee 802.3 full-duplex flow control (automatic pause frame generation or software-programmed pause frame generation and recognition) ? programmable maximum frame length supports jumbo frames (up to 9.6 kbytes) and ieee std. 802.1? virtual local area network (vlan) tags and priority ? vlan insertion and deletion ? per-frame vlan control word or default vlan for each etsec ? extracted vlan control word passed to software separately ? retransmission following a collision ? crc generation and verification of inbound/outbound frames ? programmable ethernet preamble insertion and extraction of up to 7 bytes ? mac address recognition: ? exact match on primary and vi rtual 48-bit unicast addresses
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 7 overview ? vrrp and hsrp support for seamless router fail-over ? up to 16 exact-match mac addresses supported ? broadcast address (accept/reject) ? hash table match on up to 512 multicast addresses ? promiscuous mode ? buffer descriptors backward compatible with mpc8260 and mpc860t 10/100 ethernet programming models ? rmon statistics support ? 10-kbyte internal transmit and 2-kbyte receive fifos ? mii management interface for control and status ? ability to force allocation of header information and buffer descriptors into l2 cache ? ocean switch fabric ? full crossbar packet switch ? reorders packets from a source based on priorities ? reorders packets to bypass blocked packets ? implements starvation avoidance algorithms ? supports packets with payloads of up to 256 bytes ? integrated dma controller ? four-channel controller ? all channels accessible by both the local and remote masters ? extended dma functions (advanced chaining and striding capability) ? support for scatter and gather transfers ? misaligned transfer capability ? interrupt on completed segment, link, list, and error ? supports transfers to or from any local memory or i/o port ? selectable hardware-enforced coherency (snoop/no snoop) ? ability to start and flow control each dma channel from external 3-pin interface ? ability to launch dma from single write transaction ? two pci/pci-x controllers ? pci 2.2 and pci-x 1.0 compatible ? one 32-/64-bit pci/pci-x port with support for speeds of up to 133 mhz (maximum pci-x frequency in synchronous mode is 110 mhz) ? one 32-bit pci port with support for speeds from 16 to 66 mhz (available when the other port is in 32-bit mode) ? host and agent mode support ? 64-bit dual address cycle (dac) support ? pci-x supports multiple split transactions ? supports pci-to-memory and memory-to-pci streaming
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 8 freescale semiconductor overview ? memory prefetching of pci read accesses ? supports posting of processor-to-pci and pci-to-memory writes ? pci 3.3-v compatible ? selectable hardware-enforced coherency ? serial rapidio? interface unit ? supports rapidio? interconnect specification, revision 1.2 ? both 1x and 4x lp-serial link interfaces ? long- and short-haul electricals with selectable pre-compensation ? transmission rates of 1.25, 2.5, and 3.125 gbaud (data rates of 1.0, 2.0, and 2.5 gbps) per lane ? auto detection of 1x- and 4x-mode operation during port initialization ? link initialization and synchronization ? large and small size transport information field support selectable at initialization time ? 34-bit addressing ? up to 256 bytes data payload ? all transaction flows and priorities ? atomic set/clr/inc/dec for read-modify-write operations ? generation of io_read_home and flush with data for accessing cache-coherent data at a remote memory system ? receiver-controlled flow control ? error detection, recovery, and time-out for packets and control symbols as required by the rapidio specification ? register and register bit extensions as descri bed in part viii (error management) of the rapidio specification ? hardware recovery only ? register support is not required for software-mediated error recovery. ? accept-all mode of operation for fail-over support ? support for rapidio error injection ? internal lp-serial and applica tion interface-level loopback modes ? memory and phy bist for at-speed production test ? rapidio-compatible message unit ? 4 kbytes of payload per message ? up to sixteen 256-byte segments per message ? two inbound data message structures within the inbox ? capable of receiving three letters at any mailbox ? two outbound data message structures within the outbox ? capable of sending three letters simultaneously ? single segment multicast to up to 32 devids ? chaining and direct modes in the outbox
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 9 overview ? single inbound doorbell message structure ? facility to accept port-write messages ? pci express interface ? pci express 1.0a compatible ? supports x8, x4, x2, and x1 link widths ? auto-detection of number of connected lanes ? selectable operation as root complex or endpoint ? both 32- and 64-bit addressing ? 256-byte maximum payload size ? virtual channel 0 only ? traffic class 0 only ? full 64-bit decode with 32-bit wide windows ? pin multiplexing for the high speed i/o interfaces supports one of the following configurations: ? x8 pci express ? x4 pci express and 4x serial rapidio ? power management ? supports power saving modes: doze, nap, and sleep ? employs dynamic power management, which au tomatically minimizes power consumption of blocks when they are idle ? system performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter-specific events ? supports 64 reference events that can be counted on any of the eight counters ? supports duration and quantity threshold counting ? burstiness feature that permits counting of burst events with a programmable time between bursts ? triggering and chaining capability ? ability to generate an interrupt on overflow ? system access port ? uses jtag interface and a tap controller to access entire system memory map ? supports 32-bit accesses to configuration registers ? supports cache-line burst accesses to main memory ? supports large block (4-kbyte) uploads and downloads ? supports continuous bit streaming of en tire block for fast upload and download ? jtag boundary scan, designed to comply with ieee std. 1149.1?
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 10 freescale semiconductor electrical characteristics 2 electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc8548e. this device is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications. 2.1 overall dc electrical characteristics this section covers the ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage v dd ?0.3 to 1.21 v ? pll supply voltage av dd ?0.3 to 1.21 v ? core power supply for serdes transceivers sv dd ?0.3 to 1.21 v ? pad power supply for serdes transceivers xv dd ?0.3 to 1.21 v ? ddr and ddr2 dram i/o voltage gv dd ?0.3 to 2.75 ?0.3 to 1.98 v? three-speed ethernet i/o voltage lv dd (for etsec1 and etsec2) ?0.3 to 3.63 ?0.3 to 2.75 v3 tv dd (for etsec3 and etsec4) ?0.3 to 3.63 ?0.3 to 2.75 3 pci/pci-x, duart, system control and power management, i 2 c, ethernet mii management, and jtag i/o voltage ov dd ?0.3 to 3.63 v ? local bus i/o voltage bv dd ?0.3 to 3.63 ?0.3 to 2.75 v? input voltage ddr/ddr2 dram signals mv in ?0.3 to (gv dd + 0.3) v 4 ddr/ddr2 dram reference mv ref ?0.3 to (gv dd /2 + 0.3) v? three-speed ethernet i/o signals lv in tv in ?0.3 to (lv dd + 0.3) ?0.3 to (tv dd + 0.3) v4 local bus signals bv in ?0.3 to (bv dd + 0.3) ? ? duart, sysclk, system control and power management, i 2 c, ethernet mii management, and jtag signals ov in ?0.3 to (ov dd + 0.3) v 4 pci/pci-x ov in ?0.3 to (ov dd + 0.3) v 4
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 11 electrical characteristics 2.1.2 recommended operating conditions table 2 provides the recommended operating conditions fo r this device. note that the values in table 2 are the recommended and tested operating conditions. proper device operation outside these conditions is not guaranteed. storage temperature range t stg ?55 to 150 c? notes: 1. functional and tested operating conditions are given in table 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. the ?0.3 to 2.75 v range is for ddr and ?0.3 to 1.98 v range is for ddr2. 3. the 3.63 v maximum is only supported when the port is configured in gmii, mii, rmii, or tbi modes; otherwise the 2.75 v maximum applies. see section 8.2, ?fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications,? for details on the recommended operating conditions per protocol. 4. (m,l,o)v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 . table 2. recommended operating conditions characteristic symbol recommended value unit notes core supply voltage v dd 1.1 v 55 mv v ? pll supply voltage av dd 1.1 v 55 mv v 1 core power supply for serdes transceivers sv dd 1.1 v 55 mv v ? pad power supply for serdes transceivers xv dd 1.1 v 55 mv v ? ddr and ddr2 dram i/o voltage gv dd 2.5 v 125 mv 1.8 v 90 mv v? three-speed ethernet i/o voltage lv dd 3.3 v 165 mv 2.5 v 125 mv v4 tv dd 3.3 v 165 mv 2.5 v 125 mv ?4 pci/pci-x, duart, system control and power management, i 2 c, ethernet mii management, and jtag i/o voltage ov dd 3.3 v 165 mv v 3 local bus i/o voltage bv dd 3.3 v 165 mv 2.5 v 125 mv v? input voltage ddr and ddr2 dram signals mv in gnd to gv dd v2 ddr and ddr2 dram reference mv ref gnd to gv dd /2 v 2 three-speed ethernet signals lv in tv in gnd to lv dd gnd to tv dd v4 local bus signals bv in gnd to bv dd v? pci, duart, sysclk, system control and power management, i 2 c, ethernet mii management, and jtag signals ov in gnd to ov dd v3 table 1. absolute maximum ratings 1 (continued) characteristic symbol max value unit notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 12 freescale semiconductor electrical characteristics figure 2 shows the undershoot and overshoot voltage s at the interfaces of this device. figure 2. overshoot/undershoot voltage for gv dd /ov dd /lv dd /bv dd /tv dd the core voltage must always be provided at nominal 1.1 v. voltage to the processor interface i/os are provided through separate sets of supply pins and must be provided at the voltages shown in table 2 . the input voltage threshold scales with respect to the associated i/o supply voltage. ov dd and lv dd based receivers are simple cmos i/o circuits and satisfy appropriate lvcmos type specifications. the ddr sdram interface uses a single-ended differential receiver referenced the externally supplied mv ref signal (nominally set to gv dd /2) as is appropriate for the sst l2 electrical signaling standard. junction temperature range tj 0 to 105 c? notes: 1. this voltage is the input to the filter discussed in section 21.2.1, ?pll power supply filtering,? and not necessarily the voltage at the av dd pin, which may be reduced from v dd by the filter. 2. caution: mv in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. caution: l/tv in must not exceed l/tv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. table 2. recommended operating conditions (continued) characteristic symbol recommended value unit notes gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% b/g/l/o/tv dd + 20% b/g/l/o/tv dd b/g/l/o/tv dd + 5% of t clock 1 1. t clock refers to the clock period associated with the respective interface: v ih v il notes: 2. please note that with the pci overshoot allowed (as specified above), the device does not fully comply with the maximum ac ratings and device protection guideline outlined in the pci rev. 2.2 standard (section 4.2.2.3). for i 2 c and jtag, t clock references sysclk. for ddr, t clock references mclk. for etsec, t clock references ec_gtx_clk125. for lbiu, t clock references lclk. for pci, t clock references pci n _clk or sysclk. for serdes, t clock references sd_ref_clk.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 13 electrical characteristics 2.1.3 output driver characteristics table 3 provides information on the characteristics of the output driver strengths. the values are preliminary estimates. 2.2 power sequencing the device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. these requirements are as follows for power-up: 1. v dd , av dd _ n , bv dd , lv dd , ov dd , sv dd , tv dd , xv dd 2. gv dd all supplies must be at their stable values within 50 ms. note items on the same line have no orderi ng requirement with respect to one another. items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. table 3. output drive capability driver type programmable output impedance ( ) supply vo l ta g e notes local bus interface utilities signals 25 25 bv dd = 3.3 v bv dd = 2.5 v 1 45(default) 45(default) bv dd = 3.3 v bv dd = 2.5 v pci signals 25 ov dd = 3.3 v 2 45(default) ddr signal 18 36 (half strength mode) gv dd = 2.5 v 3 ddr2 signal 18 36 (half strength mode) gv dd = 1.8 v 3 tsec/10/100 signals 45 l/tv dd = 2.5/3.3 v ? duart, system control, jtag 45 ov dd = 3.3 v ? i2c 150 ov dd = 3.3 v ? notes: 1. the drive strength of the local bus interface is determined by the configuration of the appropriate bits in porimpscr. 2. the drive strength of the pci interface is determined by the setting of the pci_gnt1 signal at reset. 3. the drive strength of the ddr interface in half-strength mode is at t j = 105 c and at gv dd (min).
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 14 freescale semiconductor power characteristics note in order to guarantee mcke low duri ng power-up, the above sequencing for gv dd is required. if there is no concern about any of the ddr signals being in an indeterminate state during power-up, then the sequencing for gv dd is not required. note from a system standpoint, if any of the i/o power supplies ramp prior to the v dd core supply, the i/os associated w ith that i/o supply may drive a logic one or zero during power-up, and extra current may be drawn by the device. 3 power characteristics the estimated typical power dissipation for the core complex bus (ccb) versus the core frequency for this family of powerquicc iii devices is shown in table 4 . 4 input clocks 4.1 system clock timing table 5 provides the system clock (sysclk) ac timing specifications for the mpc8548e. table 4. mpc8548e power dissipation ccb frequency 1 core frequency sleep 2 typical-65 3 typical-105 4 maximum 5 unit 400 800 2.7 4.6 7.5 8.1 w 1000 2.7 5.0 7.9 8.5 w 1200 2.7 5.4 8.3 8.9 500 1500 11.5 13.6 16.5 18.6 w 533 1333 6.2 7.9 10.8 12.8 w notes: 1. ccb frequency is the soc platform frequency, which corresponds to the ddr data rate. 2. sleep is based on v dd = 1.1 v, t j = 65 c. 3. typical-65 is based on v dd = 1.1 v, t j = 65 c, running dhrystone. 4. typical-105 is based on v dd = 1.1 v, t j = 105 c, running dhrystone. 5. maximum is based on v dd = 1.1 v, t j = 105 c, running a smoke test. table 5. sysclk ac timing specifications at recommended operating conditions (see ta b l e 2 ) with ov dd = 3.3 v 165 mv . parameter/condition symbol min typ max unit notes sysclk frequency f sysclk 16 ? 133 mhz 1, 6, 7, 8 sysclk cycle time t sysclk 7.5 ? 60 ns 6, 7, 8
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 15 input clocks 4.2 real time clock timing the rtc input is sampled by the platform clock (ccb clock). the output of the sampling latch is then used as an input to the counters of the pic and the timebase unit of the e500. there is no jitter specification. the minimum pulse width of the rtc signal should be greater than 2x the period of the ccb clock. that is, minimum clock high time is 2 t ccb , and minimum clock low time is 2 t ccb . there is no minimum rtc frequency; rtc may be grounded if not needed. sysclk rise and fall time t kh , t kl 0.6 1.0 1.2 ns 2 sysclk duty cycle t khk /t sysclk 40 ? 60 % 3 sysclk jitter ? ? ? 150 ps 4, 5 notes: 1. caution: the ccb clock to sysclk ratio and e500 core to ccb clock ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb clock frequency do not exceed their respective maximum or minimum operating frequencies.refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2. rise and fall times for sysclk are measured at 0.6 and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. the sysclk driver?s closed loop jitter bandwidth should be <500 khz at ?20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track sysclk drivers with the specified jitter. 6. this parameter has been adjusted slower according to the workaround for device erratum gen 13. 7. for spread spectrum clocking. guidelines are + 0% to ?1% down spread at modulation rate between 20 and 60 khz on sysclk. 8. system with operating core frequency less than 1200 mhz must limit sysclk frequency to 100 mhz maximum.. table 5. sysclk ac timing specifications (continued) at recommended operating conditions (see ta b l e 2 ) with ov dd = 3.3 v 165 mv . parameter/condition symbol min typ max unit notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 16 freescale semiconductor input clocks 4.3 etsec gigabit reference clock timing table 6 provides the etsec gigabit reference clocks (ec_gtx_clk125) ac timing specifications for the mpc8548e. 4.4 pci/pci-x reference clock timing when the pci/pci-x controller is configured for asynchronous operation, the reference clock for the pci/pci-x controller is not the sysclk input, but instead the pci n _clk. table 7 provides the pci/pci-x reference clock ac timing specifications for the mpc8548e. table 6. ec_gtx_clk125 ac timing specifications parameter/condition symbol min typ max unit notes ec_gtx_clk125 frequency f g125 ?125?mhz? ec_gtx_clk125 cycle time t g125 ?8?ns ec_gtx_clk125 rise and fall time l/tvdd = 2.5 v l/tvdd = 3.3 v t g125r , t g125f ?? 0.75 1.0 ns 1 ec_gtx_clk125 duty cycle gmii, tbi 1000base-t for rgmii, rtbi t g125h /t g125 45 47 ? 55 53 %2, 3 notes: 1. rise and fall times for ec_gtx_clk125 are measured from 0.5 and 2.0 v for l/tv dd = 2.5 v, and from 0.6 and 2.7 v for l/tv dd = 3.3 v. 2. timing is guaranteed by design and characterization. 3. ec_gtx_clk125 is used to generate the gtx clock tsec n _gtx_clk for the etsec transmitter with 2% degradation. ec_gtx_clk125 duty cycle can be loosened from 47/53% as long as the phy device can tolerate the duty cycle generated by the tsec n _ gtx_clk. see section 8.2.6, ?rgmii and rtbi ac timing specifications,? for duty cycle for 10base-t and 100base-t reference clock. table 7. pci n _clk ac timing specifications at recommended operating conditions (see ta b l e 2 ) with ov dd = 3.3 v 165 mv . parameter/condition symbol min typ max unit notes pci n _clk frequency f pciclk 16 ? 133 mhz ? pci n _clk cycle time t pciclk 7.5 ? 60 ns ? pci n _clk rise and fall time t pcikh , t pcikl 0.6 1.0 2.1 ns 1, 2 pci n _clk duty cycle t pcikhkl /t pciclk 40 ? 60 % 2 notes: 1. rise and fall times for sysclk are measured at 0.6 and 2.7 v. 2. timing is guaranteed by design and characterization.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 17 input clocks 4.5 platform to fifo restrictions please note the following fifo maximum speed restrictions based on platform speed. for fifo gmii mode: fifo tx/rx clock frequency <= platform clock frequency/4.2 for example, if the platform frequency is 533 mhz, the fifo tx/rx clock frequency should be no more than 127 mhz for fifo encoded mode: fifo tx/rx clock frequency <= platform clock frequency/4.2 for example, if the platform frequency is 533 mhz, the fifo tx/rx clock frequency should be no more than 167 mhz. 4.6 platform frequency requirements for pci-express and serial rapidio the ccb clock frequency must be considered for proper operation of the high-speed pci-express and serial rapidio interfaces as described below. for proper pci express operation, the ccb clock frequency must be greater than: 527 mhz (pci-express link width) 8 see mpc8548erm, rev. 2 , powerquicc? iii integrated processor family reference manual, section 18.1.3.2, ?link width,? for pci express interface width details. for proper serial rapidio operation, the ccb clock frequency must be greater than: 2 (0.80) (serial rapidio interface frequency) (serial rapidio link width) 64 see mpc8548erm, rev. 2 , powerquicc? iii integrated processor family reference manual, section 17.4, ?1x/4x lp-serial signal descriptions,? for serial rapidio interface width and frequency details. 4.7 other input clocks for information on the input clocks of other functional blocks of the platform see the specific section of this document.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 18 freescale semiconductor reset initialization 5 reset initialization this section describes the ac electrical specifications for the reset initialization timing requirements of the mpc8548e. table 8 provides the reset initialization ac timing specifications for the ddr sdram component(s). table 9 provides the pll lock times. 5.1 power-on ramp rate this section describes the ac electrical specifications for the power-on ramp rate requirements. table 10 provides the power supply ramp rate specifications. table 8. reset initialization timing specifications parameter/condition min max unit notes required assertion time of hreset 100 ? s? minimum assertion time for sreset 3 ? sysclks 1 pll input setup time with stable sysclk before hreset negation 100 ? s? input setup time for por configs (other than pll config) with respect to negation of hreset 4 ? sysclks 1 input hold time for all por configs (including pll config) with respect to negation of hreset 2 ? sysclks 1 maximum valid-to-high impedance time for actively driven por configs with respect to negation of hreset ? 5 sysclks 1 note: 1. sysclk is the primary clock input for the mpc8548e. table 9. pll lock times parameter/condition min max unit core and platform pll lock times ? 100 s local bus pll lock time ? 50 s pci/pci-x bus pll lock time ? 50 s table 10. power supply ramp rate parameter min max unit notes required ramp rate for mvref ? 545 volts/sec 1 required ramp rate for vdd/xvdd/svdd ? 545 volts/sec 1 note: 1. ramp rate is specified as a linear ramp. if non-linear (e.g. exponential), ramp rate from near zero to 400 mv is most critic al as this range might falsely trigger the esd circuitry.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 19 ddr and ddr2 sdram 6 ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the mpc8548e. note that gv dd (typ) = 2.5 v for ddr sdram, and gv dd (typ) = 1.8 v for ddr2 sdram. 6.1 ddr sdram dc electrical characteristics table 11 provides the recommended operating conditions for the ddr2 sdram controller of the mpc8548e when gv dd (typ) = 1.8 v . table 12 provides the ddr2 i/o capacitance when gv dd (typ) = 1.8 v. table 11. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 1.71 1.89 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ?0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref +0.125 gv dd +0.3 v ? input low voltage v il ?0.3 mv ref ? 0.125 v ? output leakage current i oz ?50 50 a4 output high current (v out = 1.420 v) i oh ?13.4 ? ma ? output low current (v out = 0.280 v) i ol 13.4 ? ma ? notes: 1. gv dd is expected to be within 50 mv of the dram v dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 12. ddr2 sdram capacitance for gv dd (typ)=1.8 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs, dqs c io 68pf1 delta input/output capacitance: dq, dqs, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 1.8 v 0.090 v, f = 1 mhz, t a = 25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 20 freescale semiconductor ddr and ddr2 sdram table 13 provides the recommended operating conditi ons for the ddr sdram controller when gv dd (typ) = 2.5 v . table 14 provides the ddr i/o capacitance when gv dd (typ) = 2.5 v. table 15 provides the current draw characteristics for mv ref . table 13. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.15 gv dd + 0.3 v ? input low voltage v il ?0.3 mv ref ? 0.15 v ? output leakage current i oz ?50 50 a4 output high current (v out = 1.95 v) i oh ?16.2 ? ma ? output low current (v out = 0.35 v) i ol 16.2 ? ma ? notes: 1. gv dd is expected to be within 50 mv of the dram v dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 14. ddr sdram capacitance for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs c io 68pf1 delta input/output capacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a =25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v. table 15. current draw characteristics for mv ref parameter/condition symbol min max unit notes current draw for mv ref i mvref ? 500 a1 note: 1. the voltage regulator for mv ref must be able to supply up to 500 a current.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 21 ddr and ddr2 sdram 6.2 ddr sdram ac electrical characteristics this section provides the ac electrical characteristics for the ddr sdram interface. the ddr controller supports both ddr1 and ddr2 memories. ddr1 is supported with the following ac timings at data rates of 333 mhz. ddr2 is supported with the following ac timings at data rates down to 333 mhz. 6.2.1 ddr sdram input ac timing specifications table 16 provides the input ac timing specifications for the ddr sdram when gv dd (typ) = 1.8 v. table 17 provides the input ac timing specifications for the ddr sdram when gv dd (typ) = 2.5 v. table 18 provides the input ac timing specifications for the ddr sdram interface. table 16. ddr2 sdram input ac timing specifications for 1.8-v interface at recommended operating conditions parameter symbol min max unit ac input low voltage v il ?mv ref ? 0.25 v ac input high voltage v ih mv ref + 0.25 ? v table 17. ddr sdram input ac timing specifications for 2.5-v interface at recommended operating conditions. parameter symbol min max unit ac input low voltage v il ?mv ref ? 0.31 v ac input high voltage v ih mv ref + 0.31 ? v table 18. ddr sdram input ac timing specifications at recommended operating conditions. parameter symbol min max unit notes controller skew for mdqs?mdq/mecc 533 mhz 400 mhz 333 mhz t ciskew ?300 ?365 ?390 300 365 390 ps 1, 2 notes: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit that will be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew . this can be determined by the following equation: t diskew = (t/4 ? abs(t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew .
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 22 freescale semiconductor ddr and ddr2 sdram 6.2.2 ddr sdram output ac timing specifications table 19. ddr sdram output ac timing specifications at recommended operating conditions. parameter symbol 1 min max unit notes mck[n] cycle time, mck[ n ]/mck [ n ] crossing t mck 3.75 6 ns 2 addr/cmd output setup with respect to mck 533 mhz 400 mhz 333 mhz t ddkhas 1.48 1.95 2.40 ? ? ? ns 3 addr/cmd output hold with respect to mck 533 mhz 400 mhz 333 mhz t ddkhax 1.48 1.95 2.40 ? ? ? ns 3 mcs [ n ] output setup with respect to mck 533 mhz 400 mhz 333 mhz t ddkhcs 1.48 1.95 2.40 ? ? ? ns 3 mcs [ n ] output hold with respect to mck 533 mhz 400 mhz 333 mhz t ddkhcx 1.48 1.95 2.40 ? ? ? ns 3 mck to mdqs skew t ddkhmh ?0.6 0.6 ns 4 mdq/mecc/mdm output setup with respect to mdqs 533 mhz 400 mhz 333 mhz t ddkhds, t ddklds 538 700 900 ? ? ? ps 5 mdq/mecc/mdm output hold with respect to mdqs 533 mhz 400 mhz 333 mhz t ddkhdx, t ddkldx 538 700 900 ? ? ? ps 5 mdqs preamble start t ddkhmp ?0.5 t mck ? 0.6 ?0.5 t mck + 0.6 ns 6
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 23 ddr and ddr2 sdram note for the addr/cmd setup and hold specifications in table 19 , it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. figure 3 shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 3. timing diagram for tddkhmh mdqs epilogue end t ddkhme ?0.6 0.6 ns 6 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck[ n ] clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the mdqs override bits (called wr_data_delay) in the timing_cfg_2 register. this will typically be set to the same delay as in ddr_sdram_clk_cntl[clk_adjust]. the timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. see the mpc8548e powerquicc? iii integrated processor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck[ n ] at the pins of the microprocessor. note that t ddkhmp follows the symbol conventions described in note 1. table 19. ddr sdram output ac timing specifications (continued) at recommended operating conditions. parameter symbol 1 min max unit notes t ddkhmhmax) = 0.6 ns mdqs mck [ n ] mck[ n ] t mck t ddkhmh(min) = ?0.6 ns mdqs
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 24 freescale semiconductor ddr and ddr2 sdram figure 4 shows the ddr sdram output timing diagram.+ figure 4. ddr sdram output timing diagram figure 5 provides the ac test load for the ddr bus. figure 5. ddr ac test load addr/cmd t ddkhas , t ddkhcs t ddklds t ddkhds mdq[x] mdqs[ n ] mck [ n ] mck[ n ] t mck t ddkldx t ddkhdx d1 d0 t ddkhax , t ddkhcx write a0 noop t ddkhme t ddkhmp t ddkhmh output z 0 = 50 gv dd /2 r l = 50
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 25 duart 7duart this section describes the dc and ac electri cal specifications for the duart interface of the mpc8548e. 7.1 duart dc electrical characteristics table 20 provides the dc electrical characteristics for the duart interface. 7.2 duart ac electrical specifications table 21 provides the ac timing parameters for the duart interface. table 20. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 1 = 0 v or v in = v dd) i in ?5 a high-level output voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.4v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 21. duart ac timing specifications parameter value unit notes minimum baud rate f ccb /1,048,576 baud 1, 2 maximum baud rate f ccb /16 baud 1, 2, 3 oversample rate 16 ? 1, 4 notes: 1. guaranteed by design. 2. f ccb refers to the internal platform clock. 3. actual attainable baud rate will be limited by the latency of interrupt processing. 4. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 26 freescale semiconductor enhanced three-speed ethernet (etsec) 8 enhanced three-speed ethernet (etsec) this section provides the ac and dc electrical char acteristics for the enhanced three-speed ethernet controller. the electrical characteristics for mdio and mdc are specified in section 9, ?ethernet management interface electrical characteristics.? 8.1 enhanced three-speed ethernet controller (etsec) (10/100/1gb mbps)?gmii/mii/tbi/rgmii/rtbi/rmii electrical characteristics the electrical characteristics specified here apply to all gigabit media independent interface (gmii), media independent interface (mii), ten-bit interface (tbi), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), and reduced media independent interface (rmii) signals except management data i nput/output (mdio) and management data clock (mdc). the rgmii and rtbi interfaces are defined for 2.5 v, while the gmii, mii, and tbi interfaces can be operated at 3.3 or 2.5 v. the gmii, mii, or tbi interface timing is compliant with the ieee 802.3. the rgmii and rtbi interfaces follow the reduced gigabit media-independent interface (rgmii) specification version 1.3 (12/10/2000). the rmii interface follows the rmii consortium rmii specification version 1.2 (3/20/1998). the electrical characteristics for mdio and mdc are specified in section 9, ?ethernet management interface electrical characteristics.? 8.1.1 etsec dc electrical characteristics all gmii, mii, tbi, rgmii, rmii, and rtbi drivers and receivers comply with the dc parametric attributes specified in table 22 and table 23 . the rgmii and rtbi signals are based on a 2.5-v cmos interface voltage as defined by jedec eia/jesd8-5. table 22. gmii, mii, rmii, and tbi dc electrical characteristics parameter symbol min max unit notes supply voltage 3.3 v lv dd tv dd 3.13 3.47 v 1, 2 output high voltage (lv dd /tv dd = min, i oh = ?4.0 ma) v oh 2.40 lv dd /tv dd + 0.3 v ? output low voltage (lv dd /tv dd = min, i ol = 4.0 ma) v ol gnd 0.50 v ? input high voltage v ih 2.0 lv dd /tv dd + 0.3 v ? input low voltage v il ?0.3 0.90 v ? input high current (v in = lv dd , v in = tv dd )i ih ?40 a 1, 2, 3 input low current (v in = gnd) i il ?600 ? a? notes: 1. lv dd supports etsecs 1 and 2. 2. tv dd supports etsecs 3 and 4. 3. the symbol v in , in this case, represents the lv in and tv in symbols referenced in ta b l e 1 and ta b l e 2 .
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 27 enhanced three-speed ethernet (etsec) 8.2 fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications the ac timing specifications for fifo, gmii, mii, tbi, rgmii, rmii, and rtbi are presented in this section. 8.2.1 fifo ac specifications the basis for the ac specifications for the etsec?s fifo modes is the double data rate rgmii and rtbi specifications, since they have similar performances and are described in a source-synchronous fashion like fifo modes. however, the fifo interface provide s deliberate skew between the transmitted data and source clock in gmii fashion. when the etsec is configured for fifo modes, all clocks are supplied from external sources to the relevant etsec interface. that is, the transmit clock must be applied to the etsec n ?s tsec n _tx_clk, while the receive clock must be applied to pin tsec n _rx_clk. the etsec internally uses the transmit clock to synchronously generate tr ansmit data and outputs an echoed copy of the transmit clock back out onto the tsec n _gtx_clk pin (while transmit data appears on tsec n _txd[7:0], for example). it is intended that external receivers capture etsec transmit data using the clock on tsec n _gtx_clk as a source- synchronous timing reference. typically, the cloc k edge that launched the data can be used, since the clock is delayed by the etsec to allow acceptable set-up margin at the receiver. note that there is relationship between the maximum fifo speed and the platform speed. for more information see section 4.5, ?platform to fifo restrictions.? table 23. gmii, mii, rmii, tbi, rgmii, rtbi, and fifo dc electrical characteristics parameters symbol min max unit notes supply voltage 2.5 v lv dd /tv dd 2.37 2.63 v 1, 2 output high voltage (lv dd /tv dd = min, i oh = ?1.0 ma) v oh 2.00 lv dd /tv dd + 0.3 v ? output low voltage (lv dd /tv dd = min, i ol = 1.0 ma) v ol gnd ?0.3 0.40 v ? input high voltage v ih 1.70 lv dd /tv dd + 0.3 v ? input low voltage v il ?0.3 0.90 v ? input high current (v in = lv dd , v in = tv dd )i ih ?10 a 1, 2, 3 input low current (v in = gnd) i il ?15 ? a3 notes: 1. lv dd supports etsecs 1 and 2. 2. tv dd supports etsecs 3 and 4. 3. note that the symbol v in , in this case, represents the lv in and tv in symbols referenced in ta b l e 1 and ta b l e 2 .
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 28 freescale semiconductor enhanced three-speed ethernet (etsec) a summary of the fifo ac specifications appears in table 24 and table 25 . timing diagrams for fifo appear in figure 6 and figure 7 . figure 6. fifo transmit ac timing diagram table 24. fifo mode transmit ac timing specification parameter/condition symbol min typ max unit tx_clk, gtx_clk clock period t fit 5.3 8.0 100 ns tx_clk, gtx_clk duty cycle t fith /t fit 45 50 55 % tx_clk, gtx_clk peak-to-peak jitter t fitj ??250ps rise time tx_clk (20%?80%) t fitr ? ? 0.75 ns fall time tx_clk (80%?20%) t fitf ? ? 0.75 ns fifo data txd[7:0], tx_er, tx_en setup time to gtx_clk t fitdv 2.0 ? ? ns gtx_clk to fifo data txd[7:0], tx_er, tx_en hold time t fitdx 0.5 ? 3.0 ns table 25. fifo mode receive ac timing specification parameter/condition symbol min typ max unit rx_clk clock period t fir 5.3 8.0 100 ns rx_clk duty cycle t firh /t fir 45 50 55 % rx_clk peak-to-peak jitter t firj ??250ps rise time rx_clk (20%?80%) t firr ? ? 0.75 ns fall time rx_clk (80%?20%) t firf ? ? 0.75 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t firdv 1.5 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t firdx 0.5 ? ? ns note: 1. the minimum cycle period of the tx_clk and rx_clk is dependent on the maximum platform frequency of t he speed bins the part belongs to as well as the fifo mode under operation. refer to section 4.5, ?platform to fifo restrictions.? t fit t fith t fitf txd[7:0] tx_en gtx_clk tx_er t fitr t fitdv t fitdx
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 29 enhanced three-speed ethernet (etsec) figure 7. fifo receive ac timing diagram 8.2.2 gmii ac timing specifications this section describes the gmii transmit and receive ac timing specifications. 8.2.2.1 gmii transmit ac timing specifications table 26 provides the gmii transmit ac timing specifications. table 26. gmii transmit ac timing specifications parameter/condition symbol 1 min typ max unit gmii data txd[7:0], tx_er, tx_en setup time t gtkhdv 2.5 ? ? ns gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx 0.5 ? 5.0 ns gtx_clk data clock rise time (20%?80%) t gtxr 2 ??1.0ns gtx_clk data clock fall time (80%?20%) t gtxf 2 ??1.0ns notes: 1. the symbols used for timing specifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that , in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. t fir t firh t firf t firr rx_clk rxd[7:0] rx_dv rx_er valid data t firdv t firdx
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 30 freescale semiconductor enhanced three-speed ethernet (etsec) figure 8 shows the gmii transmit ac timing diagram. figure 8. gmii transmit ac timing diagram 8.2.2.2 gmii receive ac timing specifications table 27 provides the gmii receive ac timing specifications. figure 9 provides the ac test load for etsec. figure 9. etsec ac test load table 27. gmii receive ac timing specifications parameter/condition symbol 1 min typ max unit rx_clk clock period t grx ?8.0?ns rx_clk duty cycle t grxh /t grx 35 ? 75 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0??ns rx_clk clock rise (20%-80%) t grxr 2 ??1.0ns rx_clk clock fall time (80%-20%) t grxf 2 ??1.0ns notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf t gtkhdv tx_en tx_er output z 0 = 50 lv dd /2 r l = 50
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 31 enhanced three-speed ethernet (etsec) figure 10 shows the gmii receive ac timing diagram. figure 10. gmii receive ac timing diagram 8.2.3 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 8.2.3.1 mii transmit ac timing specifications table 28 provides the mii transmit ac timing specifications. table 28. mii transmit ac timing specifications parameter/condition symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx 2 ?400?ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise (20%?80%) t mtxr 2 1.0 ? 4.0 ns tx_clk data clock fall (80%?20%) t mtxf 2 1.0 ? 4.0 ns notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 32 freescale semiconductor enhanced three-speed ethernet (etsec) figure 11 shows the mii transmit ac timing diagram. figure 11. mii transmit ac timing diagram 8.2.3.2 mii receive ac timing specifications table 29 provides the mii receive ac timing specifications. figure 12 provides the ac test load for etsec. figure 12. etsec ac test load table 29. mii receive ac timing specifications parameter/condition symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx 2 ?400?ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise (20%?80%) t mrxr 2 1.0 ? 4.0 ns rx_clk clock fall time (80%?20%) t mrxf 2 1.0 ? 4.0 ns notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er output z 0 = 50 lv dd /2 r l = 50
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 33 enhanced three-speed ethernet (etsec) figure 13 shows the mii receive ac timing diagram. figure 13. mii receive ac timing diagram 8.2.4 tbi ac timing specifications this section describes the tbi trans mit and receive ac timing specifications. 8.2.4.1 tbi transmit ac timing specifications table 30 provides the tbi transmit ac timing specifications. table 30. tbi transmit ac timing specifications parameter/condition symbol 1 min typ max unit tcg[9:0] setup time gtx_clk going high t ttkhdv 2.0 ? ? ns tcg[9:0] hold time from gtx_clk going high t ttkhdx 1.0 ? ? ns gtx_clk rise (20%?80%) t ttxr 2 ??1.0ns gtx_clk fall time (80%?20%) t ttxf 2 ??1.0ns notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state )(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid state (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. rx_clk rxd[3:0] t mrdxkl t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 34 freescale semiconductor enhanced three-speed ethernet (etsec) figure 14 shows the tbi transmit ac timing diagram. figure 14. tbi transmit ac timing diagram 8.2.4.2 tbi receive ac timing specifications table 31 provides the tbi receive ac timing specifications. table 31. tbi receive ac timing specifications parameter/condition symbol 1 min typ max unit tsec n _rx_clk[0:1] clock period t trx ? 16.0 ? ns tsec n _rx_clk[0:1] skew t sktrx 7.5 ? 8.5 ns tsec n _rx_clk[0:1] duty cycle t trxh /t trx 40 ? 60 % rcg[9:0] setup time to rising tsec n _rx_clk t trdvkh 2.5 ? ? ns rcg[9:0] hold time to rising tsec n _rx_clk t trdxkh 1.5 ? ? ns tsec n _rx_clk[0:1] clock rise time (20%?80%) t trxr 2 0.7 ? 2.4 ns tsec n _rx_clk[0:1] clock fall time (80%?20%) t trxf 2 0.7 ? 2.4 ns notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). 2. guaranteed by design. gtx_clk tcg[9:0] t ttxr t ttx t ttxh t ttxr t ttxf t ttkhdv t ttkhdx t ttxf
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 35 enhanced three-speed ethernet (etsec) figure 15 shows the tbi receive ac timing diagram. figure 15. tbi receive ac timing diagram 8.2.5 tbi single-clock mode ac specifications when the etsec is configured for tbi modes, all cloc ks are supplied from external sources to the relevant etsec interface. in single-clock tbi mode, when tbicon[clksel] = 1, a 125-mhz tbi receive clock is supplied on the tsec n _rx_clk pin (no receive clock is used on tsec n _tx_clk in this mode, whereas for the dual-clock mode this is the pma1 receive clock). the 125-mhz transmit clock is applied on the tsec_gtx_clk125 pin in all tbi modes. a summary of the single-clock tbi mode ac specifications for receive appears in table 32 . table 32. tbi single-clock mode receive ac timing specification parameter/condition symbol min typ max unit rx_clk clock period t trrx 7.5 8.0 8.5 ns rx_clk duty cycle t trrh/trrx 40 50 60 % rx_clk peak-to-peak jitter t trrj ??250ps rise time rx_clk (20%?80%) t trrr ??1.0ns fall time rx_clk (80%?20%) t trrf ??1.0ns rcg[9:0] setup time to rx_clk rising edge t trrdvkh 2.0 ? ? ns rcg[9:0] hold time to rx_clk rising edge t trrdxkh 1.0 ? ? ns tsec n _rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh tsec n _rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh valid data valid data
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 36 freescale semiconductor enhanced three-speed ethernet (etsec) a timing diagram for tbi receive appears in figure 16 . . figure 16. tbi single-clock mode receive ac timing diagram 8.2.6 rgmii and rtbi ac timing specifications table 33 presents the rgmii and rtbi ac timing specifications. table 33. rgmii and rtbi ac timing specifications parameter/condition symbol 1 min typ max unit data to clock output skew (at transmitter) t skrgt 5 ?500 6 0 500 6 ps data to clock input skew (at receiver) 2 t skrgt 1.0 ? 2.8 ns clock period 3 t rgt 5 7.2 8.0 8.8 ns duty cycle for 10base-t and 100base-tx 3, 4 t rgth /t rgt 5 45 50 55 % rise time (20%?80%) t rgtr 5 ? ? 0.75 ns fall time (20%?80%) t rgtf 5 ? ? 0.75 ns notes: 1. in general, the clock reference symbol representation for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. 5. guaranteed by characterization. 6. in rev 1.0 silicon, due to errata, t skrgt is -650 ps (min) and 650 ps (max). please refer to ?etsec 10? in the device errata document. t trrx t trrh t trrf t trrr rx_clk rcg[9:0] valid data t trrdxkh t trrdvkh
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 37 enhanced three-speed ethernet (etsec) figure 17 shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 17. rgmii and rtbi ac timing and multiplexing diagrams 8.2.7 rmii ac timing specifications this section describes the rmii transmit and receive ac timing specifications. 8.2.7.1 rmii transmit ac timing specifications the rmii transmit ac timing specifications are in table 34 . table 34. rmii transmit ac timing specifications parameter/condition symbol 1 min typ max unit tsec n _tx_clk clock period t rmt 15.0 20.0 25.0 ns tsec n _tx_clk duty cycle t rmth 35 50 65 % tsec n _tx_clk peak-to-peak jitter t rmtj ??250ps rise time tsec n _tx_clk (20%?80%) t rmtr 1.0 ? 2.0 ns fall time tsec n _tx_clk (80%?20%) t rmtf 1.0 ? 2.0 ns gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 38 freescale semiconductor enhanced three-speed ethernet (etsec) figure 18 shows the rmii transmit ac timing diagram. figure 18. rmii transmit ac timing diagram 8.2.7.2 rmii receive ac timing specifications tsec n _tx_clk to rmii data txd[1:0], tx_en delay t rmtdx 1.0 ? 10.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 35. rmii receive ac timing specifications parameter/condition symbol 1 min typ max unit tsec n _tx_clk clock period t rmr 15.0 20.0 25.0 ns tsec n _tx_clk duty cycle t rmrh 35 50 65 % tsec n _tx_clk peak-to-peak jitter t rmrj ??250ps rise time tsec n _tx_clk(20%?80%) t rmrr 1.0 ? 2.0 ns fall time tsec n _tx_clk (80%?20%) t rmrf 1.0 ? 2.0 ns rxd[1:0], crs_dv, rx_er setup time to ref_clk rising edge t rmrdv 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk rising edge t rmrdx 2.0 ? ? ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 34. rmii transmit ac timing specifications (continued) parameter/condition symbol 1 min typ max unit tsec n _tx_clk txd[1:0] t rmtdx t rmt t rmth t rmtr t rmtf tx_en tx_er
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 39 ethernet management interface electrical characteristics figure 19 provides the ac test load for etsec. figure 19. etsec ac test load figure 20 shows the rmii receive ac timing diagram. figure 20. rmii receive ac timing diagram 9 ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (management data input/output) and mdc (management data clock). the electrical characteristics for gmii, rgmii, rmii, tbi, and rtbi are specified in ? section 8, ?enhanced three-speed ethernet (etsec).? 9.1 mii management dc electrical characteristics the mdc and mdio are defined to operate at a supply vo ltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 36 . table 36. mii management dc electrical characteristics parameter symbol min max unit supply voltage (3.3 v) ov dd 3.13 3.47 v output high voltage (ov dd = min, i oh = ?1.0 ma) v oh 2.10 ov dd + 0.3 v output low voltage (ov dd =min, i ol = 1.0 ma) v ol gnd 0.50 v input high voltage v ih 2.0 ? v input low voltage v il ?0.90v output z 0 = 50 lv dd /2 r l = 50
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 40 freescale semiconductor ethernet management interface electrical characteristics 9.2 mii management ac electrical specifications table 37 provides the mii management ac timing specifications. input high current (ov dd = max, v in 1 = 2.1 v) i ih ?40 a input low current (ov dd = max, v in = 0.5 v) i il ?600 ? a note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 37. mii management ac timing specifications at recommended operating conditions with ov dd is 3.3 v 5%. parameter/condition symbol 1 min typ max unit notes mdc frequency f mdc 0.72 2.5 8.3 mhz 2, 3,4 mdc period t mdc 120.5 ? 1389 ns ? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio valid t mdkhdv 16 t ccb ??ns5 mdc to mdio delay t mdkhdx (16 * t ptb_clk *8)-3 ?(16 * t ptb_clk *8)+3 ns 5 mdio to mdc setup time t mddvkh 5??ns? mdio to mdc hold time t mddxkh 0??ns? mdc rise time t mdcr ? ? 10 ns 4 mdc fall time t mdhf ?10ns4 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the etsec system clock speed, which is half of the platform frequency (f ccb ). the actual ecn_mdc output clock frequency for a specific etsec port can be programmed by configuring the mgmtclk bit field of mpc8548e ?s miimcfg register, based on the platform (ccb) clock running for the device. the formula is: platform frequency (ccb)/(2*frequency divider determined by miicfg[mgmtclk] encoding selection). for example, if miicfg[mgmtclk] = 000 and the platform (ccb) is currently running at 533 m hz, f mdc = 533/(2*4*8) = 533/64 = 8.3 mhz. that is, for a system running at a particular platform frequency (f ccb ), the ecn_mdc output clock frequency can be programmed between maximum f mdc = f ccb /64 and minimum f mdc = f ccb /448. refer to mpc8572e reference manual?s miimcfg register section for more detail.3.the maximum ecn_mdc output clock frequency is defined based on the maximum platform frequency for mpc8548e (533 mhz) divided by 64, while the minimum ecn_mdc output clock frequency is defined based on the minimum platform frequency for mpc8548e (333 mhz) divided by 448, following the formula described in note 2 above. 4. guaranteed by design. 5. t ccb is the platform (ccb) clock period. table 36. mii management dc electrical characteristics (continued) parameter symbol min max unit
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 41 local bus figure 21 shows the mii management ac timing diagram. figure 21. mii management interface timing diagram 10 local bus this section describes the dc and ac electrical specifications for the local bus interface of the mpc8548e. 10.1 local bus dc electrical characteristics table 38 provides the dc electrical characteristics for the local bus interface operating at bv dd = 3.3 v dc. table 38. local bus dc electrical characteristics (3.3 v dc) parameter symbol min max unit high-level input voltage v ih 2bv dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 1 = 0 v or v in = bv dd )i in ?5 a high-level output voltage (bv dd = min, i oh = ?2 ma) v oh 2.4 ? v low-level output voltage (bv dd = min, i ol = 2 ma) v ol ?0.4v note: 1. note that the symbol v in , in this case, represents the bv in symbol referenced in ta ble 1 and ta ble 2 . mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output)
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 42 freescale semiconductor local bus table 39 provides the dc electrical characteristics for the local bus interface operating at bv dd = 2.5 v dc. 10.2 local bus ac electrical specifications table 40 describes the timing parameters of the local bus interface at bv dd = 3.3 v. for information about the frequency range of local bus see section 19.1, ?clock ranges.? table 39. local bus dc electrical characteristics (2.5 v dc) parameter symbol min max unit high-level input voltage v ih 1.70 bv dd + 0.3 v low-level input voltage v il ?0.3 0.7 v input current (v in 1 = 0 v or v in = bv dd )i ih ?10 a i il ?15 high-level output voltage (bv dd = min, i oh = ?1 ma) v oh 2.0 ? v low-level output voltage (bv dd = min, i ol = 1 ma) v ol ?0.4v note: 1. note that the symbol v in , in this case, represents the bv in symbol referenced in ta ble 1 and ta ble 2 . table 40. local bus timing parameters (bv dd = 3.3 v)?pll enabled parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 12 ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % ? lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7, 8 input setup to local bus clock (except lgta /lupwait) t lbivkh1 1.8 ? ns 3, 4 lgta /lupwait input setup to local bus clock t lbivkh2 1.7 ? ns 3, 4 input hold from local bus clock (except lgta /lupwait) t lbixkh1 1.0 ? ns 3, 4 lgta /lupwait input hold from local bus clock t lbixkh2 1.0 ? ns 3, 4 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?2.0ns? local bus clock to data valid for lad/ldp t lbkhov2 ?2.2ns3 local bus clock to address valid for lad t lbkhov3 ?2.3ns3 local bus clock to lale assertion t lbkhov4 ?2.3ns3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.7 ? ns 3 output hold from local bus clock for lad/ldp t lbkhox2 0.7 ? ns 3 local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.5ns5
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 43 local bus table 41 describes the timing parameters of the local bus interface at bv dd = 2.5 v. local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.5ns5 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from bv dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. t lbotot is programmed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[ n ]. skew measured between complementary signals at bv dd /2. 8. guaranteed by design. table 41. local bus timing parameters (bv dd = 2.5 v)?pll enabled parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 12 ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % ? lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7, 8 input setup to local bus clock (except lgta /upwait) t lbivkh1 1.9 ? ns 3, 4 lgta /lupwait input setup to local bus clock t lbivkh2 1.8 ? ns 3, 4 input hold from local bus clock (except lgta /lupwait) t lbixkh1 1.1 ? ns 3, 4 lgta /lupwait input hold from local bus clock t lbixkh2 1.1 ? ns 3, 4 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?2.1ns? local bus clock to data valid for lad/ldp t lbkhov2 ?2.3ns3 local bus clock to address valid for lad t lbkhov3 ?2.4ns3 local bus clock to lale assertion t lbkhov4 ?2.4ns3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.8 ? ns 3 output hold from local bus clock for lad/ldp t lbkhox2 0.8 ? ns 3 table 40. local bus timing parameters (bv dd = 3.3 v)?pll enabled (continued) parameter symbol 1 min max unit notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 44 freescale semiconductor local bus figure 22 provides the ac test load for the local bus. figure 22. local bus ac test load note pll bypass mode is required when lbiu frequency is at or below 83 mhz. when lbiu operates above 83 mhz, lbiu pll is recommended to be enabled. local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.6ns5 local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.6ns5 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from bv dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. t lbotot is programmed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd /2. 8. guaranteed by design. table 41. local bus timing parameters (bv dd = 2.5 v)?pll enabled (continued) parameter symbol 1 min max unit notes output z 0 = 50 bv dd /2 r l = 50
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 45 local bus figure 23 through figure 28 show the local bus signals. figure 23. local bus signals (pll enabled) table 42 describes the timing parameters of the local bus interface at bv dd = 3.3 v with pll disabled. table 42. local bus timing parameters?pll bypassed parameter symbol 1 min max unit notes local bus cycle time t lbk 12 ? ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % ? internal launch/capture clock to lclk delay t lbkhkt 2.3 4.4 ns 8 input setup to local bus clock (except lgta /lupwait) t lbivkh1 6.2 ? ns 4, 5 lgta /lupwait input setup to local bus clock t lbivkl2 6.1 ? ns 4, 5 input hold from local bus clock (except lgta /lupwait) t lbixkh1 ?1.8 ? ns 4, 5 lgta /lupwait input hold from local bus clock t lbixkl2 ?1.3 ? ns 4, 5 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbklov1 ? ?0.3 ns ? output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov1 t lbkhov2 t lbkhov3 lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh1 t lbivkh1 t lbivkh2 t lbixkh2 t lbkhox1 t lbkhoz1 t lbkhox2 t lbkhoz2 input signal: lgta t lbotot t lbkhoz2 t lbkhox2 t lbkhov4 lupwait
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 46 freescale semiconductor local bus local bus clock to data valid for lad/ldp t lbklov2 ? ?0.1 ns 4 local bus clock to address valid for lad t lbklov3 ?0ns4 local bus clock to lale assertion t lbklov4 ?0ns4 output hold from local bus clock (except lad/ldp and lale) t lbklox1 -3.7 ? ns 4 output hold from local bus clock for lad/ldp t lbklox2 -3.7 ? ns 4 local bus clock to output high impedance (except lad/ldp and lale) t lbkloz1 ?0.2ns7 local bus clock to output high impedance for lad/ldp t lbkloz2 ?0.2ns7 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to local bus clock for pll bypass mode. timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes lclk by t lbkhkt . 3. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[ n ]. skew measured between complementary signals at bv dd /2. 4. all signals are measured from bv dd /2 of the rising edge of local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 3.3-v signaling levels. 5. input timings are measured at the pin. 6. the value of t lbotot is the measurement of the minimum time between the negation of lale and any change in lad. 7. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. guaranteed by characterization. 9. guaranteed by design. table 42. local bus timing parameters?pll bypassed (continued) parameter symbol 1 min max unit notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 47 local bus figure 24. local bus signals (pll bypass mode) note in pll bypass mode, lclk[ n ] is the inverted version of the internal clock with the delay of t lbkhkt . in this mode, signals are launched at the rising edge of the internal clock and are captured at falling edge of the internal clock with the exception of lgta /lupwait (which is captured on the rising edge of the internal clock). output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbklov2 lclk[ n ] input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] lale t lbixkh1 input signal: lgta output (address) signal: lad[0:31] t lbivkh1 t lbixkl2 t lbivkl2 t lbklox1 t lbkloz2 t lbotot internal launch/capture clock t lbklox2 t lbklov1 t lbklov3 t lbkloz1 t lbkhkt t lbklov4 lupwait
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 48 freescale semiconductor local bus figure 25. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 gpcm mode input signal: lgta
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 49 local bus figure 26. local bus si gnals, gpcm/upm signals for lccr[clkdiv] = 4 (pll bypass mode) t lbivkh1 t lbixkl2 internal launch/capture clock upm mode input signal: lupwait t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov1 t lbkloz1 lclk t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 50 freescale semiconductor local bus figure 27. local bus signals, gpcm/upm signal s for lccr[clkdiv] = 8 or 16 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4 input signals: lad[0:31]/ldp[0:3] gpcm mode input signal: lgta
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 51 programmable interrupt controller figure 28. local bus signals, gpcm/upm signals for lccr[clkdiv] = 8 or 16 (pll bypass mode) 11 programmable interrupt controller in irq edge trigger mode, when an external interr upt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (sysclk periods). 12 jtag this section describes the dc and ac electrical sp ecifications for the ieee 1149.1 (jtag) interface of the mpc8548e. t lbixkl2 t lbivkh1 internal launch/capture clock upm mode input signal: lupwait t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t2 t4 input signals: lad[0:31]/ldp[0:3] lclk t lbklov1 t lbkloz1 t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 52 freescale semiconductor jtag 12.1 jtag dc electrical characteristics table 43 provides the dc electrical characteristics for the jtag interface. 12.2 jtag ac electrical specifications table 44 provides the jtag ac timing specifications as defined in figure 30 through figure 32 . table 43. jtag dc electrical characteristics parameter symbol 1 min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 1 = 0 v or v in = v dd )i in ?5 a high-level output voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.4v note: 1. note that the symbol v in , in this case, represents the ov in . table 44. jtag ac timing specifications (independent of sysclk) 1 parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 0 33.3 mhz ? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns ? jtag external clock rise and fall times t jtgr & t jtgf 02ns6 trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 0 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 20 25 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 4 4 20 25 ns 5 output hold times: boundary-scan data tdo t jtkldx t jtklox 30 30 ? ? ns 5
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 53 jtag figure 29 provides the ac test load for tdo and the boundary-scan outputs. figure 29. ac test load for the jtag interface figure 30 provides the jtag clock input timing diagram. figure 30. jtag clock input timing diagram figure 31 provides the trst timing diagram. figure 31. trst timing diagram jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 3 3 19 9 ns 5, 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load (see figure 29 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design. table 44. jtag ac timing specifications (independent of sysclk) 1 (continued) parameter symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 54 freescale semiconductor i 2 c figure 32 provides the boundary-scan timing diagram. figure 32. boundary-scan timing diagram 13 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interfaces of the mpc8548e. 13.1 i 2 c dc electrical characteristics table 45 provides the dc electrical characteristics for the i 2 c interfaces. table 45. i 2 c dc electrical characteristics parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd +0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00.2 ov dd v1 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns2 input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a3 capacitance for each i/o pin c i ?10pf? notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. refer to the mpc8548e powerquicc? iii integrated processor family reference manual , for information on the digital filter used. 3. i/o pins will obstruct the sda and scl lines if ov dd is switched off. vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 55 i 2 c 13.2 i 2 c ac electrical specifications table 46 provides the ac timing parameters for the i 2 c interfaces. table 46. i 2 c ac electrical specifications parameter symbol 1 min max unit notes scl clock frequency f i2c 0400khz? low period of the scl clock t i2cl 1.3 ? s4 high period of the scl clock t i2ch 0.6 ? s4 setup time for a repeated start condition t i2svkh 0.6 ? s4 hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s4 data setup time t i2dvkh 100 ? ns 4 data input hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 ? ? s2 data output delay time: t i2ovkl ?0.9?3 set-up time for stop condition t i2pvkh 0.6 ? s? bus free time between a stop and start condition t i2khdx 1.3 ? s? noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v? noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). 2. as a transmitter, the mpc8548e provides a delay time of at least 300 ns for the sda signal (refer to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl to avoid unintended generation of start or stop condition. when mpc8548e acts as the i 2 c bus master while transmitting, mpc8548e drives both scl and sda. as long as the load on scl and sda are balanced, mpc8548e would not cause unintended generation of start or stop condition. therefore, the 300 ns sda output delay time is not a concern. if, under some rare condition, the 300 ns sda output delay time is required for mpc8548e as transmitter, the following setting is recommended for the fdr bit field of the i2cfdr register to ensure both the desired i 2 c scl clock frequency and sda output delay time are achieved, assuming that the desired i 2 c scl clock frequency is 400 khz and the digital filter sampling rate register (i2cdfsrr) is programmed with its default setting of 0x10 (decimal 16): i 2 c source clock frequency 333 mhz 266 mhz 200 mhz 133 mhz fdr bit setting 0x2a 0x05 0x26 0x00 actual fdr divider selected 896 704 512 384 actual i 2 c scl frequency generated 371 khz 378 khz 390 khz 346 khz for the detail of i 2 c frequency calculation, refer to freescale application note an2919, determining the i 2 c frequency divider ratio for scl . note that the i 2 c source clock frequency is half of the ccb clock frequency for mpc8548e. 3. the maximum t i2dxkl has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. guaranteed by design.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 56 freescale semiconductor pci/pci-x figure 29 provides the ac test load for the i 2 c. figure 33. i 2 c ac test load figure 34 shows the ac timing diagram for the i 2 c bus. figure 34. i 2 c bus ac timing diagram 14 pci/pci-x this section describes the dc and ac electrical specifications for the pci/pci-x bus of the mpc8548e. note that the maximum pci-x freque ncy in synchronous mode is 110 mhz. 14.1 pci/pci-x dc electrical characteristics table 47 provides the dc electrical characteristics for the pci/pci-x interface. table 47. pci/pci-x dc electrical characteristics 1 parameter symbol min max unit notes high-level input voltage v ih 2ov dd + 0.3 v ? low-level input voltage v il ?0.3 0.8 v ? input current (v in = 0 v or v in = v dd )i in ?5 a2 high-level output voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.4v? notes: 1. ranges listed do not meet the full range of the dc specifications of the pci 2.2 local bus specifications . 2. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . output z 0 = 50 ov dd /2 r l = 50
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 57 pci/pci-x 14.2 pci/pci-x ac electrical specifications this section describes the general ac timing parame ters of the pci/pci-x bus. note that the clock reference clk is represented by sysclk when the pci controller is configured for asynchronous mode and by pci n _clk when it is configured for asynchronous mode. table 48 provides the pci ac timing specifications at 66 mhz. figure 35 provides the ac test load for pci and pci-x. figure 35. pci/pci-x ac test load table 48. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit notes clk to output valid t pckhov ? 6.0 ns 2, 3 output hold from clk t pckhox 2.0 ? ns 2, 10 clk to output high impedance t pckhoz ? 14 ns 2, 4, 11 input setup to clk t pcivkh 3.0 ? ns 2, 5, 10 input hold from clk t pcixkh 0 ? ns 2, 5, 10 req64 to hreset 9 setup time t pcrvrh 10 t sys ? clocks 6, 7, 11 hreset to req64 hold time t pcrhrx 050ns7, 11 hreset high to first frame assertion t pcrhfv 10 ? clocks 8, 11 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci/pci-x timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the sysclk clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci/pci-x timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. all pci signals are measured from ov dd /2 of the rising edge of sysclk or pci_clk n to 0.4 ov dd of the signal in question for 3.3-v pci signaling levels. 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. input timings are measured at the pin. 6. the timing parameter t sys indicates the minimum and maximum clk cycle times for the various specified frequencies. the system clock period must be kept within the minimum and maximum defined ranges. for values see section 19, ?clocking .? 7. the setup and hold time is with respect to the rising edge of hreset . 8. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci 2.2 local bus specifications . 9. the reset assertion timing requirement for hreset is 100 s. 10.guaranteed by characterization. 11.guaranteed by design. output z 0 = 50 lv dd /2 r l = 50
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 58 freescale semiconductor pci/pci-x figure 36 shows the pci/pci-x input ac timing conditions. figure 36. pci/pci-x input ac timing measurement conditions figure 37 shows the pci/pci-x output ac timing conditions. figure 37. pci/pci-x output ac timing measurement condition table 49 provides the pci-x ac timing specifications at 66 mhz. table 49. pci-x ac timing specifications at 66 mhz parameter symbol min max unit notes sysclk to signal valid delay t pckhov ? 3.8 ns 1, 2, 3, 7, 8 output hold from sysclk t pckhox 0.7 ? ns 1, 10 sysclk to output high impedance t pckhoz ? 7 ns 1, 4, 8, 11 input setup time to sysclk t pcivkh 1.7 ? ns 3, 5 input hold time from sysclk t pcixkh 0.5 ? ns 10 req64 to hreset setup time t pcrvrh 10 ? clocks 11 hreset to req64 hold time t pcrhrx 050ns 11 hreset high to first frame assertion t pcrhfv 10 ? clocks 9, 11 pci-x initialization pattern to hreset setup time t pcivrh 10 ? clocks 11 t pcivkh clk input t pcixkh clk output delay t pckhov high-impedance t pckhoz output
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 59 pci/pci-x table 50 provides the pci-x ac timing specifications at 133 mhz. note that the maximum pci-x freque ncy in synchronous mode is 110 mhz. hreset to pci-x initialization pattern hold time t pcrhix 050ns6, 11 notes: 1. see the timing measurement conditions in the pci-x 1.0a specification . 2. minimum times are measured at the package pin (not the test point). maximum times are measured with the test point and load circuit. 3. setup time for point-to-point signals applies to req and gnt only. all other signals are bused. 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 6. maximum value is also limited by delay to the first transaction (time for hreset high to first configuration access, t pcrhfv ). the pci-x initialization pattern control signals after the rising edge of hreset must be negated no later than two clocks before the first frame and must be floated no later than one clock before frame is asserted. 7. a pci-x device is permitted to have the minimum values shown for t pckhov and t cyc only in pci-x mode. in conventional mode, the device must meet the requirements specified in pci 2.2 for the appropriate clock frequency. 8. device must meet this specification independent of how many outputs switch simultaneously. 9. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci-x 1.0a specification. 10.guaranteed by characterization. 11.guaranteed by design. table 50. pci-x ac timing specifications at 133 mhz parameter symbol min max unit notes sysclk to signal valid delay t pckhov ? 3.8 ns 1, 2, 3, 7, 8 output hold from sysclk t pckhox 0.7 ? ns 1, 11 sysclk to output high impedance t pckhoz ? 7 ns 1, 4, 8, 12 input setup time to sysclk t pcivkh 1.2 ? ns 3, 5, 9, 11 input hold time from sysclk t pcixkh 0.5 ? ns 11 req64 to hreset setup time t pcrvrh 10 ? clocks 12 hreset to req64 hold time t pcrhrx 050ns 12 hreset high to first frame assertion t pcrhfv 10 ? clocks 10, 12 pci-x initialization pattern to hreset setup time t pcivrh 10 ? clocks 12 table 49. pci-x ac timing specifications at 66 mhz (continued) parameter symbol min max unit notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 60 freescale semiconductor high-speed serial interfaces (hssi) 15 high-speed serial interfaces (hssi) the mpc8548e features one serializer/deserializer (serdes) interface to be used for high-speed serial interconnect applications. the serdes interface can be used for pci express and/or serial rapidio data transfers. this section describes the common portion of serdes dc electrical specifications, which is the dc requirement for serdes reference clocks. the serdes da ta lane?s transmitter and receiver reference circuits are also shown. 15.1 signal terms definition the serdes utilizes differential signaling to transfer data across the serial link. this section defines terms used in the description and specification of differential signals. figure 38 shows how the signals are defined. for illustration purpose, only one serdes lane is used for the description. the figure shows a waveform for either a transmitter output (sd_tx and sd_tx ) or a receiver input (sd_rx and sd_rx ). each signal swings between a volts and b volts where a > b. using this waveform, the definitions are as follows. to simplify the illustration, the following definitions assume that the serdes transmitter and receiver opera te in a fully symmetrical differential signaling environment. 1. single-ended swing hreset to pci-x initialization pattern hold time t pcrhix 050ns6, 12 notes: 1. see the timing measurement conditions in the pci-x 1.0a specification . 2. minimum times are measured at the package pin (not the test point). maximum times are measured with the test point and load circuit. 3. setup time for point-to-point signals applies to req and gnt only. all other signals are bused. 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 6. maximum value is also limited by delay to the first transaction (time for hreset high to first configuration access, t pcrhfv ). the pci-x initialization pattern control signals after the rising edge of hreset must be negated no later than two clocks before the first frame and must be floated no later than one clock before frame is asserted. 7. a pci-x device is permitted to have the minimum values shown for t pckhov and t cyc only in pci-x mode. in conventional mode, the device must meet the requirements specified in pci 2.2 for the appropriate clock frequency. 8. device must meet this specification independent of how many outputs switch simultaneously. 9. the timing parameter t pcivkh is a minimum of 1.4 ns rather than the minimum of 1.2 ns in the pci-x 1.0a specification. 10.the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci-x 1.0a specification. 11.guaranteed by characterization. 11.guaranteed by design. table 50. pci-x ac timing specifications at 133 mhz (continued) parameter symbol min max unit notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 61 high-speed serial interfaces (hssi) the transmitter output signals and the receiver input signals sd_tx, sd_tx , sd_rx and sd_rx each have a peak-to-peak swing of a ? b volts. this is also referred as each signal wire?s single-ended swing. 2. differential output voltage, v od (or differential output swing): the differential output voltage (or swing) of the transmitter, v od , is defined as the difference of the two complimentary output voltages: v sd_tx ?v sd_tx . the v od value can be either positive or negative. 3. differential input voltage, v id (or differential input swing): the differential input voltage (or swing) of the receiver, v id , is defined as the difference of the two complimentary input voltages: v sd_rx ?v sd_rx . the v id value can be either positive or negative. 4. differential peak voltage, v diffp the peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, v diffp = |a ? b| volts. 5. differential peak-to-peak, v diffp-p since the differential output signal of the transmitter and the differential input signal of the receiver each range from a ? b to ?(a ? b) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, v diffp-p = 2 v diffp = 2 |(a ? b)| volts, which is twice of differential swing in amplitude, or twice of the differential peak. for example, the output differential peak-to-peak voltage can also be calculated as v tx-diffp-p = 2 |v od |. 6. common mode voltage, v cm the common mode voltage is equa l to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. in this example, for serdes output, v cm_out = v sd_tx + v sd_tx = (a + b)/2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. in a system, the common mode voltage may often differ from one component?s output to the other?s input. sometimes, it may be even different between the receiver input and driver output circuits within the same component. it is also referred to as the dc offset. figure 38. differential voltage definitions for transmitter or receiver differential swing, v id or v od = a ? b a volts b volts sd_tx or sd_rx sd_tx or sd_rx differential peak voltage, v diffp = |a ? b| differential peak-peak voltage, v diffpp = 2*v diffp (not shown) v cm = (a + b)/2
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 62 freescale semiconductor high-speed serial interfaces (hssi) to illustrate these definitions using real values, consider the case of a cml (current mode logic) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5 and 2.0 v. using these values, th e peak-to-peak voltage swing of each signal (td or td ) is 500 mvp-p, which is referred as the single-ended swing for each signal. in this example, since the differential signaling environment is fully symmetrical, the transmitter output?s differential swing (v od ) has the same amplitude as each signal?s single-ended swing. the differential output signal ranges between 500 and ?500 mv, in other words, v od is 500 mv in one phase and ?500 mv in the other phase. the peak differential voltage (v diffp ) is 500 mv. the peak-to-peak differential voltage (v diffp-p ) is 1000 mvp-p. 15.2 serdes reference clocks the serdes reference clock inputs are applied to an internal pll whose output creates the clock used by the corresponding serdes lanes. the serdes reference clocks inputs are sd_ref_clk and sd_ref_clk for pci express and serial rapidio. the following sections describe the serdes re ference clock requirement s and some application information. 15.2.1 serdes reference clock receiver characteristics figure 39 shows a receiver reference diagram of the serdes reference clocks. ? the supply voltage requirements for xv dd_srds2 are specified in table 1 and table 2 . ? serdes reference clock receiver reference circuit structure: ? the sd_ref_clk and sd_ref_clk are internally ac-coupled differential inputs as shown in figure 39 . each differential clock input (sd_ref_clk or sd_ref_clk ) has a 50- termination to sgnd_srds n (xcorevss) followed by on-chip ac-coupling. ? the external reference clock driver must be able to drive this termination. ? the serdes reference clock input can be eith er differential or single-ended. refer to the differential mode and single-ended mode descri ption below for further detailed requirements. ? the maximum average current requirement that also determines the common mode voltage range: ? when the serdes reference clock differential i nputs are dc coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 ma. in this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 ma (refer to th e following bullet for more detail), since the input is ac-coupled on-chip. ? this current limitation sets the maximum common m ode input voltage to be less than 0.4 v (0.4 v/50 = 8 ma) while the minimum common mode input level is 0.1 v above sgnd_srds n (xcorevss). for example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 to 16 ma (0?0.8 v), such that each phase of the differential input has a single-ended swing from 0 v to 800 mv with the common mode voltage at 400 mv. ? if the device driving the sd_ref_clk and sd_ref_clk inputs cannot drive 50 to sgnd_srds n (xcorevss) dc, or it exceeds the maximum input current limitations, then it must be ac-coupled off-chip.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 63 high-speed serial interfaces (hssi) ? the input amplitude requirement: ? this requirement is described in detail in the following sections. figure 39. receiver of serdes reference clocks 15.2.2 dc level requirement for serdes reference clocks the dc level requirement for the mpc8548e serdes reference clock inputs is different depending on the signaling mode used to connect the clock driver ch ip and serdes reference clock inputs as described below: ? differential mode ? the input amplitude of the differential cl ock must be between 400 and 1600 mv differential peak-peak (or between 200 and 800 mv differential peak). in other words, each signal wire of the differential pair must have a single-ended swing less than 800 mv and greater than 200 mv. this requirement is the same for both external dc-coupled or ac-coupled connection. ? for external dc-coupled connection, as described in section 15.2.1, ?serdes reference clock receiver characteristics,? the maximum average current requirements sets the requirement for average voltage (common mode volta ge) to be between 100 and 400 mv. figure 40 shows the serdes reference clock input requirement for dc-coupled connection scheme. ? for external ac-coupled connection, there is no common mode voltage requirement for the clock driver. since the external ac-coupling capac itor blocks the dc level, the clock driver and the serdes reference clock receiver operate in different command mode voltages. the serdes reference clock receiver in this connec tion scheme has its common mode voltage set to sgnd_srds n . each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (sgnd_srds n ). figure 41 shows the serdes reference clock input requirement for ac-coupled connection scheme. ? single-ended mode ? the reference clock can also be single-ended. the sd_ref_clk input amplitude (single-ended swing) must be between 400 and 800 mv peak-to-peak (from v min to v max ) with sd_ref_clk either left unconnected or tied to ground. ? the sd_ref_clk input average volta ge must be between 200 and 400 mv. figure 42 shows the serdes reference clock input requirement for single-ended signaling mode. input amp 50 50 sd_ref_clk sd_ref_clk
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 64 freescale semiconductor high-speed serial interfaces (hssi) ? to meet the input amplitude requirement, the re ference clock inputs might need to be dc- or ac-coupled externally. for the best noise performance, the reference of the clock could be dc- or ac-coupled into the unused phase (sd_ref_clk ) through the same source impedance as the clock input (sd_ref_clk) in use. figure 40. differential reference clock input dc requirements (external dc-coupled) figure 41. differential reference clock input dc requirements (external ac-coupled) figure 42. single-ended reference clock input dc requirements 15.2.3 interfacing with other differential signaling levels ? with on-chip termination to sgnd_srdsn (xcorevss), the differential reference clocks inputs are hcsl (high-speed current steering logic) compatible dc-coupled. ? many other low voltage differential type outputs li ke lvds (low voltage differential signaling) can be used but may need to be ac-coupled due to the limited common mode input range allowed (100 to 400 mv) for dc-coupled connection. sd_ref_clk sd_ref_clk v max < 800 mv v min > 0v 100 mv < v cm < 400 mv 200 mv < input amplitude or differential peak < 800 mv sd_ref_clk sd_ref_clk sd_ref_clk v cm 200 mv < input amplitude or differential peak < 800 mv v max < v cm + 400 mv v min > v cm ? 400 mv sd_ref_clk sd_ref_clk 400 mv < sd_ref_clk input amplitude < 800 mv 0 v
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 65 high-speed serial interfaces (hssi) ? lvpecl outputs can produce signal with too large amplitude and may need to be dc-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to ac-coupling. note figure 43 through figure 46 below are for conceptual reference only. due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it?s very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. they might also vary from one vendor to the other. therefore, freescale semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. the system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the mpc8548e serdes reference clock receiver requirement provided in this document. figure 43 shows the serdes reference clock connection reference circuits for hcsl type clock driver. it assumes that the dc levels of the clock driver chip is compatible with mpc8548e serdes reference clock input?s dc requirement. figure 43. dc-coupled differential connection with hcsl clock driver (reference only) figure 44 shows the serdes reference clock connection reference circuits for lvds type clock driver. since lvds clock driver?s common mode voltage is higher than the mpc8548e serdes reference clock input?s allowed range (100 to 400mv), ac-coupled connection scheme must be used. it assumes the lvds output driver features 50- termination resistor. it also assumes that the lvds transmitter establishes its own common mode level without rely ing on the receiver or other external component. 50 50 sd_ref_clk sd_ref_clk clock driver 100 differential pwb trace clock driver vendor dependent source termination resistor clk_out clk_out hcsl clk driver chip 33 33 total 50 . assume clock driver?s output impedance is about 16 . mpc8548e clk_out serdes refer. clk receiver clock driver
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 66 freescale semiconductor high-speed serial interfaces (hssi) figure 44. ac-coupled differential connection with lvds clock driver (reference only) figure 45 shows the serdes reference clock connection refe rence circuits for lvpecl type clock driver. since lvpecl driver?s dc levels (both common mode voltages and output swing) are incompatible with the mpc8548e serdes reference clock input?s dc requirement, ac-coupling has to be used. figure 45 assumes that the lvpecl clock driver?s output impedance is 50 . r1 is used to dc-bias the lvpecl outputs prior to ac-coupling. its value could be ranged from 140 to 240 depending on the clock driver vendor?s requirement. r2 is used together with the serdes reference clock receiver?s 50- termination resistor to attenuate the lvpecl output?s differential peak level such that it meets the mpc8548e serdes reference clock?s differential input amplitude requi rement (between 200 and 800 mv differential peak). for example, if the lvpecl output?s differential peak is 900 mv and the desired serdes reference clock input amplitude is selected as 600 mv, the attenuation factor is 0.67, which requires r2 = 25 . consult a clock driver chip manufacturer to verify whether this connection scheme is comp atible with a particular clock driver chip. figure 45. ac-coupled differential connection with lvpecl clock driver (reference only) sd_ref_clk sd_ref_clk clock driver 100 differential pwb trace clk_out clk_out lvds clk driver chip 10 nf 10 nf mpc8548e serdes refer. clk receiver 50 50 clock driver sd_ref_clk sd_ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvpecl clk driver chip r2 r2 mpc8548e 10 nf 10 nf clk_out clk_out r2 r2 r1 clock driver 50 50 r1
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 67 high-speed serial interfaces (hssi) figure 46 shows the serdes reference clock connection refe rence circuits for a single-ended clock driver. it assumes the dc levels of the clock driver are compatible with the mpc8548e serdes reference clock input?s dc requirement. figure 46. single-ended connection (reference only) 15.2.4 ac requirements for serdes reference clocks the clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. phase noise less than 100 khz ca n be tracked by the pll and data recovery loops and is less of a problem. phase noise above 15 mhz is fi ltered by the pll. the most problematic phase noise occurs in the 1?15-mhz range. the source impedance of the clock driver should be 50 to match the transmission line and reduce reflections which are a source of noise to the system. the detailed ac requirements of the serdes referen ce clocks is defined by each interface protocol based on application usage. refer to the foll owing sections for detailed information: ? section 16.2, ?ac requirements for pci express serdes clocks? ? section 17.2, ?ac requirements for serial rapidio sd_ref_clk and sd_ref_clk? 15.2.4.1 spread spectrum clock sd_ref_clk/sd_ref_clk are designed to work with a spread spectrum clock (+0% to ?0.5% spreading at 30?33 khz rate is allowed), assuming both e nds have same reference clock. for better results, a source without significant unintended modulation should be used. sd_ref_clk sd_ref_clk 100 differential pwb trace clock driver clk_out single-ended clk driver chip mpc8548e 33 total 50 . assume clock driver?s output impedance is about 16 . 50 serdes refer. clk receiver 50 50
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 68 freescale semiconductor pci express 15.3 serdes transmitter and receiver reference circuits figure 47 shows the reference circuits for serdes data lane?s transmitter and receiver. figure 47. serdes transmitter and receiver reference circuits the dc and ac specification of serdes data lanes ar e defined in each interface protocol section below (pci express, serial rapid io, or sgmii) in this document based on the application usage: ? section 16, ?pci express? ? section 17, ?serial rapidio? note that external an ac coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in the specification of each protocol section. 16 pci express this section describes the dc and ac electrical specifications for the pci express bus of the mpc8548e. 16.1 dc requirements for pci express sd_ref_clk and sd_ref_clk for more information, see section 15.2, ?serdes reference clocks.? 16.2 ac requirements for pci express serdes clocks table 51 lists the ac requirements for the pci express serdes clocks. table 51. sd_ref_clk and sd_ref_clk ac requirements symbol parameter description min typ max unit notes t ref refclk cycle time ? 10 ? ns 1 t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles. ? ? 100 ps ? t refpj phase jitter. deviation in edge location with respect to mean edge location. ?50 ? 50 ps ? note: 1. typical based on pci express specification 2.0 . sd_tx n sd_tx n sd_rx n sd_rx n 50 receiver transmitter 50 50 50
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 69 pci express 16.3 clocking dependencies the ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. this is specified to a llow bit rate clock sources with a 300 ppm tolerance. 16.4 physical layer specifications the following is a summary of the specifications for the physical layer of pci express on this device. for further details as well as the specifications of the transport and data link layer refer to pci express base specification. rev. 1.0a . 16.4.1 differential transmitter (tx) output table 52 defines the specifications for the differential output at all transmitters (txs). the parameters are specified at the component pins. table 52. differential transmitter (tx) output specifications symbol parameter min nom max unit comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. v tx-diffp-p differential peak-to-peak output voltage 0.8 ? 1.2 v v tx-diffp-p = 2*|v tx-d+ ? v tx-d? |. see note 2. v tx-de-ratio de- emphasized differential output voltage (ratio) ?3.0 ?3.5 ?4.0 db ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. see note 2. t tx-eye minimum tx eye width 0.70 ? ? ui the maximum transmitter jitter can be derived as t tx-max-jitter = 1 ? t tx-eye = 0.3 ui. see notes 2 and 3. t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median. ? ? 0.15 ui jitter is defined as the measurement variation of the crossing points (v tx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2 and 3. t tx-rise , t tx-fall d+/d? tx output rise/fall time 0.125 ? ? ui see notes 2 and 5. v tx-cm-acp rms ac peak common mode output voltage ??20mvv tx-cm-acp = rms(|v txd+ + v txd? |/2 ? v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d? |/2. see note 2.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 70 freescale semiconductor pci express v tx-cm-dc-active- idle-delta absolute delta of dc common mode voltage during l0 and electrical idle 0?100mv|v tx-cm-dc (during l0) + v tx-cm-idle-dc (during electrical idle) | <= 100 mv v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d? |/2 [l0] v tx-cm-idle-dc = dc (avg) of |v tx-d+ +v tx-d? |/2 [electrical idle] see note 2. v tx-cm-dc-line-delta absolute delta of dc common mode between d+ and d? 0?25mv|v tx-cm-dc-d+ ? v tx-cm-dc-d? | <= 25 mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d? = dc (avg) of |v tx-d? |. see note 2. v tx-idle-diffp electrical idle differential peak output voltage 0?20mvv tx-idle-diffp = |v tx-idle-d+ ? v tx-idle-d? | <= 20 mv. see note 2. v tx-rcv-detect the amount of voltage change allowed during receiver detection ? ? 600 mv the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. see note 6. v tx-dc-cm the tx dc common mode voltage 0 ? 3.6 v the allowed dc common mode voltage under any conditions. see note 6. i tx-short tx short circuit current limit ? ? 90 ma the total current the transmitter can provide when shorted to its ground t tx-idle-min minimum time spent in electrical idle 50 ? ui minimum time a transmitter must be in electrical idle utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set t tx-idle-set-to-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set ? ? 20 ui after sending an electrical idle ordered set, the transmitter must meet all electrical idle specifications within this time. this is considered a debounce time for the transmitter to meet electrical idle after transitioning from l0. t tx-idle-to-diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition ? ? 20 ui maximum time to meet all tx specifications when transitioning from electrical idle to sending differential data. this is considered a debounce time for the tx to meet all tx specifications after leaving electrical idle rl tx-diff differential return loss 12 ? ? db measured over 50 mhz to 1.25 ghz. see note 4. rl tx-cm common mode return loss 6 ? ? db measured over 50 mhz to 1.25 ghz. see note 4. table 52. differential transmitter (tx) output specifications (continued) symbol parameter min nom max unit comments
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 71 pci express 16.4.2 transmitter compliance eye diagrams the tx eye diagram in figure 48 is specified using the passive compliance/test measurement load (see figure 50 ) in place of any real pci express interconnect +rx component. there are two eye diagrams that must be met for the transmitter. both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. the exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. the eye diagram must be valid for any 250 consecutive uis. z tx-diff-dc dc differential tx impedance 80 100 120 tx dc differential mode low impedance z tx-dc transmitter dc impedance 40 ? ? required tx d+ as well as d? dc impedance during all states l tx-skew lane-to-lane output skew ? ? 500 +2ui ps static skew between any two transmitter lanes within a single link c tx ac coupling capacitor 75 ? 200 nf all transmitters shall be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. see note 8. t crosslink crosslink random timeout 0 ? 1 ms this random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. see note 7. notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timing and voltage compliance test load as shown in figure 50 and measured over any 250 consecutive tx uis. (also refer to the transmitter compliance eye diagram shown in figure 48 .) 3. a t tx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of t tx-jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes?see figure 50 ). note that the series capacitors c tx is optional for the return loss measurement. 5. measured between 20%?80% at transmitter package pins into a test load as shown in figure 50 for both v tx-d+ and v tx-d? . 6. see section 4.3.1.8 of the pci express base specifications rev 1.0a. 7. see section 4.2.6.3 of the pci express base specifications rev 1.0a. 8. mpc8548e serdes transmitter does not have ctx built in. an external ac coupling capacitor is required. table 52. differential transmitter (tx) output specifications (continued) symbol parameter min nom max unit comments
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 72 freescale semiconductor pci express a recovered tx ui is calculated over 3500 consecutive un it intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algorithm using a minimization merit function (for example, least squares and median deviation fits). figure 48. minimum transmitter timing and voltage output compliance specifications 16.4.3 differential receiver (rx) input specifications table 53 defines the specifications for the differential i nput at all receivers (rxs). the parameters are specified at the component pins. table 53. differential receiver (rx) input specifications symbol parameter min nom max unit comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. v rx-diffp-p differential peak-to-peak input voltage 0.175 ? 1.200 v v rx-diffp-p = 2*|v rx-d+ ? v rx-d? |. see note 2. v tx-diff = 0 mv (d+ d? crossing point) [de-emphasized bit] 0.07 ui = ui ? 0.3 ui (j tx-total-max ) 566 mv (3 db) >= v tx-diffp-p-min >= 505 mv (4 db) [transition bit] v tx-diffp-p-min = 800 mv v rx-diff = 0 mv (d+ d? crossing point) [transition bit] v tx-diffp-p-min = 800 mv
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 73 pci express t rx-eye minimum receiver eye width 0.4 ? ? ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter =1 ? t rx-eye = 0.6 ui. see notes 2 and 3. t rx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median ? ? 0.3 ui jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2, 3, and 7. v rx-cm-acp ac peak common mode input voltage ??150mvv rx-cm-acp = |v rxd+ ? v rxd- |/2 + v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ + v rx-d? |/2. see note 2. rl rx-diff differential return loss 15 ? ? db measured over 50 mhz to 1.25 ghz with the d+ and d? lines biased at +300 mv and ?300 mv, respectively. see note 4. rl rx-cm common mode return loss 6 ? ? db measured over 50 mhz to 1.25 ghz with the d+ and d? lines biased at 0 v. see note 4. z rx-diff-dc dc differential input impedance 80 100 120 rx dc differential mode impedance. see note 5. z rx-dc dc input impedance 40 50 60 required rx d+ as well as d? dc impedance (50 20% tolerance). see notes 2 and 5. z rx-high-imp-dc powered down dc input impedance 200 k ? ? required rx d+ as well as d? dc impedance when the receiver terminations do not have power. see note 6. v rx-idle-det-diffp-p electrical idle detect threshold 65 ? 175 mv v rx-idle-det-diffp-p = 2*|v rx-d+ -v rx-d? |. measured at the package pins of the receiver t rx-idle-det-diff- entertime unexpected electrical idle enter detect threshold integration time ? ? 10 ms an unexpected electrical idle (v rx-diffp-p < v rx-idle-det-diffp-p ) must be recognized no longer than t rx-idle-det-diff-entering to signal an unexpected idle condition. table 53. differential receiver (rx) input specifications (continued) symbol parameter min nom max unit comments
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 74 freescale semiconductor pci express 16.5 receiver compliance eye diagrams the rx eye diagram in figure 49 is specified using the passive compliance/test measurement load (see figure 50 ) in place of any real pci express rx component. note: in general, the minimum receiver eye diagram measured with the compliance/test measurement load (see figure 50 ) will be larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real pci express component. the degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real pci express component to vary in impedance from the co mpliance/test measurement load. the input receiver eye diagram is implementation specific and is not specified. rx component designer should provide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in figure 49 ) expected at the input receiver based on some ad equate combination of system simulations and the return loss measured looking into the rx package and silicon. the rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. l tx-skew total skew ? ? 20 ns skew across all lanes on a link. this includes variation in the length of skp ordered set (for example, com and one to five symbols) at the rx as well as any delay differences arising from the interconnect itself. notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 50 should be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram shown in figure 49 ). if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the t rx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4. the receiver input impedance shall result in a differential return loss greater than or equal to 15 db with the d+ line bias ed to 300 mv and the d? line biased to ?{300 mv and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements for is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes?see figure 50 ). note: that the series capacitors ctx is optional for the return loss measurement. 5. impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 6. the rx dc common mode impedance that exists when no power is present or fundamental reset is asserted. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. 7. it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algorithm using a minimization merit function. least squares and median deviation fits have worked well with experimental and simulated data. table 53. differential receiver (rx) input specifications (continued) symbol parameter min nom max unit comments
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 75 pci express the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive un it intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note the reference impedance for return loss measurements is 50. to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes?see figure 50 ). note that the series capacitors, ctx, are optional for the return loss measurement. figure 49. minimum receiver eye timing and voltage compliance specification 16.5.1 compliance test and measurement load the ac timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in figure 50 . note the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from d+ and d? not being exac tly matched in length at the package pin boundary. figure 50. compliance test/measurement load v rx-diff = 0 mv (d+ d? crossing point) v rx-diff = 0 mv (d+ d? crossing point) v rx-diffp-p-min > 175 mv 0.4 ui = t rx-eye-min tx silicon + package c = c tx c = c tx r = 50 r = 50 d+ package pin d? package pin d+ package pin
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 76 freescale semiconductor serial rapidio 17 serial rapidio this section describes the dc and ac electrical specifications for the rapidio interface of the mpc8548e, for the lp-serial physical layer. the electrical specifications cover both single- and multiple-lane links. two transmitters (short and long run) and a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 gbaud. two transmitter specifications allow for solutions ra nging from simple board-to-board interconnect to driving two connectors across a backplane. a single rece iver specification is given that will accept signals from both the short- and long-run transmitter specifications. the short-run transmitter should be used mainly for chip-to-chip connections on either the same printed-circuit board or across a single connector. this covers the case where connections are made to a mezzanine (daughter) card. the minimum swings of the short-run specification reduce the overall power used by the transceivers. the long-run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. this allows a user to drive signals acr oss two connectors and a backplane. the specifications allow a distance of at least 50 cm at all baud rates. all unit intervals are specified with a tolerance of 100 ppm. the worst case frequency difference between any transmit and receive clock will be 200 ppm. to ensure interoperability between drivers and receivers of different vendors and technologies, ac coupling at the receiver input must be used. 17.1 dc requirements for serial rapidio sd_ref_clk and sd_ref_clk for more information, see section 15.2, ?serdes reference clocks.? 17.2 ac requirements for serial rapidio sd_ref_clk and sd_ref_clk table 54 lists the serial rapidio sd_ref_clk and sd_ref_clk ac requirements. table 54. sd_ref_clk and sd_ref_clk ac requirements symbol parameter description min typ max unit comments t ref refclk cycle time ? 10(8) ? ns 8 ns applies only to serial rapidio with 125-mhz reference clock t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles. ? ? 80 ps ? t refpj phase jitter. deviation in edge location with respect to mean edge location. ?40 ? 40 ps ?
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 77 serial rapidio 17.3 signal definitions lp-serial links use differential signaling. this s ection defines terms used in the description and specification of differential signals. figure 51 shows how the signals are defined. the figures show waveforms for either a transmitter output (td and td ) or a receiver input (rd and rd ). each signal swings between a volts and b volts where a > b. using these waveforms, the definitions are as follows: 1. the transmitter output signals and the receiver input signals td, td , rd, and rd each have a peak-to-peak swing of a ? b volts. 2. the differential output signal of the transmitter, v od , is defined as v td ?v td . 3. the differential input signal of the receiver, v id , is defined as v rd ?v rd . 4. the differential output signal of the transmitter and the differential input signal of the receiver each range from a ? b to ?(a ? b) volts. 5. the peak value of the differential transmitte r output signal and the differential receiver input signal is a ? b volts. 6. the peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 (a ? b) volts. figure 51. differential peak?peak voltage of transmitter or receiver to illustrate these definitions using real values, consider the case of a cml (current mode logic) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5 and 2.0 v. using these values, th e peak-to-peak voltage swing of the signals td and td is 500 mvp-p. the differential output signal ranges between 500 and ?500 mv. the peak differential voltage is 500 mv. the peak-to-peak differential voltage is 1000 mvp-p. 17.4 equalization with the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. effects such as inter-symbol interference (i si) or data dependent jitter are produced. this loss can be large enough to degrade the eye opening at the r eceiver beyond what is allowed in the specification. to negate a portion of these effects, equalization can be used. the most common equalization techniques that can be used are: ? a passive high pass filter network placed at the receiver. this is often referred to as passive equalization. ? the use of active circuits in the receiver. this is often referred to as adaptive equalization. differential peak-to-peak = 2 (a ? b) a volts td or rd td or rd b volts
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 78 freescale semiconductor serial rapidio 17.5 explanatory note on transmitter and receiver specifications ac electrical specifications are given for transmitter and receiver. long- and short-run interfaces at three baud rates (a total of six cases) are described. the parameters for the ac electrical specifications are guided by the xaui electrical interface specified in clause 47 of ieee 802.3ae-2002. xaui has similar application goals to serial rapidio, as described in section 8.1. the goal of this standard is that electrical designs for serial ra pidio can reuse electrical designs for xaui, suitably modified for applications at the baud intervals and reaches described herein. 17.6 transmitter specifications lp-serial transmitter electrical and timing specifications are stated in the text and tables of this section. the differential return loss, s11, of the transmitter in each case shall be better than: ? ?10 db for (baud frequency)/10 < freq(f) < 625 mhz, and ? ?10 db + 10log(f/625 mhz) db for 625 mhz freq(f) baud frequency the reference impedance for the differential return loss measurements is 100- resistive. differential return loss includes contributions from on-chip circ uitry, chip packaging, and any off-chip components related to the driver. the output impedance requirement applies to all valid output levels. it is recommended that the 20%?80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps. it is recommended that the timing skew at the output of an lp-serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 gb, 20 ps at 2.50 gb, and 15 ps at 3.125 gb. table 55. short run transmitter ac timing specifications?1.25 gbaud characteristic symbol range unit notes min max output voltage v o ?0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p ? deterministic jitter j d ?0.17ui p-p ? tot a l j itt e r j t ?0.35ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps 100 ppm
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 79 serial rapidio table 56. short run transmitter ac timing specifications?2.5 gbaud characteristic symbol range unit notes min max output voltage v o ?0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p ? deterministic jitter j d ?0.17ui p-p ? tot a l j itt e r j t ?0.35ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps 100 ppm table 57. short run transmitter ac timing specifications?3.125 gbaud characteristic symbol range unit notes min max output voltage v o ?0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mvp-p ? deterministic jitter j d ?0.17ui p-p ? tot a l j itt e r j t ?0.35ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps 100 ppm table 58. long run transmitter ac timing specifications?1.25 gbaud characteristic symbol range unit notes min max output voltage v o ?0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mvp-p ? deterministic jitter j d ?0.17ui p-p ? tot a l j itt e r j t ?0.35ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps 100 ppm
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 80 freescale semiconductor serial rapidio for each baud rate at which an lp-serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown in figure 52 with the parameters specified in table 61 when measured at the out put pins of the device and the device is driving a 100- 5% differential resistive load. the output eye pattern of an lp-serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized. table 59. long run transmitter ac timing specifications?2.5 gbaud characteristic symbol range unit notes min max output voltage v o ?0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mvp-p ? deterministic jitter j d ?0.17ui p-p ? tot a l j itt e r j t ?0.35ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps 100 ppm table 60. long run transmitter ac timing specifications?3.125 gbaud characteristic symbol range unit notes min max output voltage v o ?0.40 2.30 v voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mvp-p ? deterministic jitter j d ?0.17ui p-p ? tot a l j itt e r j t ?0.35ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps 100 ppm
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 81 serial rapidio figure 52. transmitter output compliance mask 17.7 receiver specifications lp-serial receiver electrical and timing specifications are stated in the text and tables of this section. receiver input impedance shall result in a differential return loss better that 10 db and a common mode return loss better than 6 db from 100 mhz to (0.8) (baud frequency). this includes contributions from on-chip circuitry, the chip package, and any off-ch ip components related to the receiver. ac coupling components are included in this requirement. the refe rence impedance for return loss measurements is 100- resistive for differential return loss and 25- resistive for common mode. table 61. transmitter differential output eye diagram parameters transmitter type v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud short range 250 500 0.175 0.39 1.25 gbaud long range 400 800 0.175 0.39 2.5 gbaud short range 250 500 0.175 0.39 2.5 gbaud long range 400 800 0.175 0.39 3.125 gbaud short range 250 500 0.175 0.39 3.125 gbaud long range 400 800 0.175 0.39 0 v diff min v diff max ?v diff min ?v diff max 0b1-b1 time in ui transmitter differential output voltage a1-a
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 82 freescale semiconductor serial rapidio table 62. receiver ac timing specifications?1.25 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mvp-p measured at receiver deterministic jitter tolerance j d 0.37 ? ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ? ui p-p measured at receiver total jitter tolerance 1 j t 0.65 ? ui p-p measured at receiver multiple input skew s mi ? 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber ? 10 ?12 ?? unit interval ui 800 800 ps 100 ppm note: 1. total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 53 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects. table 63. receiver ac timing specifications?2.5 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mvp-p measured at receiver deterministic jitter tolerance j d 0.37 ? ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ? ui p-p measured at receiver total jitter tolerance 1 j t 0.65 ? ui p-p measured at receiver multiple input skew s mi ? 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber ? 10 ?12 ? unit interval ui 400 400 ps 100 ppm note: 1. total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 53 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 83 serial rapidio figure 53. single frequency sinusoidal jitter limits table 64. receiver ac timing specifications?3.125 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mvp-p measured at receiver deterministic jitter tolerance j d 0.37 ? ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ? ui p-p measured at receiver total jitter tolerance 1 j t 0.65 ? ui p-p measured at receiver multiple input skew s mi ? 22 ns skew at the receiver input between lanes of a multilane link bit error rate ber ? 10 -12 ? unit interval ui 320 320 ps 100 ppm note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 53 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. 8.5 ui p-p 0.10 ui p-p sinusoidal jitter amplitude 22.1 khz 1.875 mhz 20 mhz frequency
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 84 freescale semiconductor serial rapidio 17.8 receiver eye diagrams for each baud rate at which an lp-serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate specification ( table 62 , table 63 , table 64 ) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver input compliance mask shown in figure 54 with the parameters specified in table 65 . the eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100- 5% differential resistive load. figure 54. receiver input compliance mask 17.9 measurement and test requirements since the lp-serial electrical specification are gui ded by the xaui electrical interface specified in clause 47 of ieee std. 802.3ae-2002, the measurement and test requirements de fined here are similarly guided by clause 47. in addition, the cjpat test patte rn defined in annex 48a of ieee std. 802.3ae-2002 table 65. receiver input compliance mask parameters exclusive of sinusoidal jitter receiver type v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud 100 800 0.275 0.400 2.5 gbaud 100 800 0.275 0.400 3.125 gbaud 100 800 0.275 0.400 1 0 v diff max ?v diff max v diff min ?v diff min time (ui) receiver differential input voltage 0 ab 1-b1-a
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 85 serial rapidio is specified as the test pattern for use in eye pattern and jitter measurements. annex 48b of ieee std. 802.3ae-2002 is recommended as a reference for additional information on jitter test methods. 17.9.1 eye template measurements for the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 db point at (baud frequency)/1667 is applied to the jitter. the data patter n for template measurements is the continuous jitter test pattern (cjpat) defined in anne x 48a of ieee 802.3ae. all lanes of the lp-serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. four lane imple mentations shall use cjpat as defined in annex 48a. single lane implementations shall use the cjpat sequence specifi ed in annex 48a for transmission on lane 0. the amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10 ?12 . the eye pattern shall be measured with ac coupling and the compliance template centered at 0 v differential. the left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. the load for this test shall be 100- resistive 5% differential to 2.5 ghz. 17.9.2 jitter test measurements for the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 db point at (baud frequency)/1667 is applied to the jitter. the da ta pattern for jitter measurements is the continuous jit ter test pattern (cjpat) pattern defined in annex 48a of ieee 802.3ae. all lane s of the lp-serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. four lane implementations shall use cjpat as defined in annex 48a. si ngle lane implementations shall use the cjpat sequence specified in annex 48a fo r transmission on lane 0. jitter shall be measured with ac coupling and at 0 v differential. jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be performed with a test pro cedure resulting in a ber curve such as that described in annex 48b of ieee 802.3ae. 17.9.3 transmit jitter transmit jitter is measured at the driver output when terminated into a load of 100 resistive 5% differential to 2.5 ghz. 17.9.4 jitter tolerance jitter tolerance is measured at the receiver using a jitte r tolerance test signal. this signal is obtained by first producing the sum of deterministic and random jitter defined in section 17.7, ?receiver specifications,? and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening of the receive template shown in figure 54 and table 65 . note that for this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter) about the mean zero crossing. eye template meas urement requirements are as defined above. random jitter is calibrated using a high pass filter with a low frequency corner at 20 mhz and a 20 db/decade roll-off below this. the required sinusoidal jitter specified in section 17.7, ?receiver specifications,? is then added to the signal and the test load is replaced by the receiver being tested.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 86 freescale semiconductor package description 18 package description this section details package paramete rs, pin assignments, and dimensions. 18.1 package parameters the package parameters for both the hicte fc-cbga and fc-pbga are as provided in table 66 . table 66. package parameters parameter cbga 1 pbga 2 package outline 29 mm 29 mm 29 mm 29 mm interconnects 783 783 ball pitch 1 mm 1 mm ball diameter (typical) 0.6 mm 0.6 mm solder ball 62% sn 36% pb 2% ag 62% sn 36% pb 2% ag solder ball (lead-free) 95% sn 4.5% ag 0.5% cu 96.5% sn 3.5% ag notes: 1. the hicte fc-cbga package is available on only version 2.0 of the device. 2. the fc-pbga package is available on only version 2.1.1 and 2.1.2 of the device.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 87 package description 18.2 mechanical dimensions of the hicte fc-cbga and fc-pbga with full lid figure 55 shows the mechanical dimensions and botto m surface nomenclature for both the mpc8548e hicte fc-cbga and fc-pbga package with full lid. figure 55. mechanical dimensions and bottom surface nomenclature of the hicte fc-cbga and fc-pbga with full lid notes: 1. all d imensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. 6. all dimensions are symmetric across the package center lines unless dimensioned otherwise. 7. package code summary: ?pbga 8423 ?cbga 5112
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 88 freescale semiconductor package description 18.3 pinout listings note the dma_dack [0:1] and test_sel/test_sel pins must be set to a proper state during por configuration. please refer to the pinlist table of the individual device for more details. for mpc8548/47/45, gpios are still available on pci1_ad[63:32]/pc2_ad[31:0] pins if they are not used for pci functionality. for mpc8545/43, etsec does not support 16 bit fifo mode. table 67 provides the pinout listing for the mpc8548e 783 fc-pbga package. table 67. mpc8548e pinout listing signal package pin number pin type power supply notes pci1 and pci2 (one 64-bit or two 32-bit) pci1_ad[63:32]/pci2_ad[31:0] ab14, ac15, aa15, y16, w16, ab16, ac16, aa16, ae17, aa18, w18, ac17, ad16, ae16, y17, ac18, ab18, aa19, ab19, ab21, aa20, ac20, ab20, ab22, ac22, ad21, ab23, af23, ad23, ae23, ac23, ac24 i/o ov dd 17 pci1_ad[31:0] ah6, ae7, af7, ag7, ah7, af8, ah8, ae9, ah9, ac10, ab10, ad10, ag10, aa10, ah10, aa11, ab12, ae12, ag12, ah12, ab13, aa12, ac13, ae13, y14, w13, ag13, v14, ah13, ac14, y15, ab15 i/o ov dd 17 pci1_c_be [7:4]/pci2_c_be [3:0] af15, ad14, ae15, ad15 i/o ov dd 17 pci1_c_be [3:0] af9, ad11, y12, y13 i/o ov dd 17 pci1_par64/pci2_par w15 i/o ov dd pci1_gnt [4:1] ag6, ae6, af5, ah5 o ov dd 5, 9, 35 pci1_gnt0 ag5 i/o ov dd ? pci1_irdy af11 i/o ov dd 2 pci1_par ad12 i/o ov dd ? pci1_perr ac12 i/o ov dd 2 pci1_serr v13 i/o ov dd 2, 4 pci1_stop w12 i/o ov dd 2 pci1_trdy ag11 i/o ov dd 2
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 89 package description pci1_req [4:1] ah2, ag4, ag3, ah4 i ov dd ? ? ? ? ? pci1_req0 ah3 i/o ov dd ? pci1_clk ah26 i ov dd 39 pci1_devsel ah11 i/o ov dd 2 pci1_frame ae11 i/o ov dd 2 pci1_idsel ag9 i ov dd ? pci1_req64 /pci2_frame af14 i/o ov dd 2, 5, 10 pci1_ack64 /pci2_devsel v15 i/o ov dd 2 pci2_clk ae28 i ov dd 39 pci2_irdy ad26 i/o ov dd 2 pci2_perr ad25 i/o ov dd 2 pci2_gnt [4:1] ae26, ag24, af25, ae25 o ov dd 5, 9, 35 pci2_gnt0 ag25 i/o ov dd ? pci2_serr ad24 i/o ov dd 2, 4 pci2_stop af24 i/o ov dd 2 pci2_trdy ad27 i/o ov dd 2 pci2_req [4:1] ad28, ae27, w17, af26 i ov dd ? pci2_req0 ah25 i/o ov dd ? ddr sdram memory interface mdq[0:63] l18, j18, k14, l13, l19, m18, l15, l14, a17, b17, a13, b12, c18, b18, b13, a12, h18, f18, j14, f15, k19, j19, h16, k15, d17, g16, k13, d14, d18, f17, f14, e14, a7, a6, d5, a4, c8, d7, b5, b4, a2, b1, d1, e4, a3, b2, d2, e3, f3, g4, j5, k5, f6, g5, j6, k4, j1, k2, m5, m3, j3, j2, l1, m6 i/o gv dd ? mecc[0:7] h13, f13, f11, c11, j13, g13, d12, m12 i/o gv dd ? mdm[0:8] m17, c16, k17, e16, b6, c4, h4, k1, e13 o gv dd ? mdqs[0:8] m15, a16, g17, g14, a5, d3, h1, l2, c13 i/o gv dd ? mdqs [0:8] l17, b16, j16, h14, c6, c2, h3, l4, d13 i/o gv dd ? ma[0:15] a8, f9, d9, b9, a9, l10, m10, h10, k10, g10, b8, e10, b10, g6, a10, l11 ogv dd ? mba[0:2] f7, j7, m11 o gv dd ? table 67. mpc8548e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 90 freescale semiconductor package description mwe e7 o gv dd ? mcas h7 o gv dd ? mras l8 o gv dd ? mcke[0:3] f10, c10, j11, h11 o gv dd 11 mcs [0:3] k8, j8, g8, f8 o gv dd ? mck[0:5] h9, b15, g2, m9, a14, f1 o gv dd ? mck [0:5] j9, a15, g1, l9, b14, f2 o gv dd ? modt[0:3] e6, k6, l7, m7 o gv dd ? mdic[0:1] a19, b19 i/o gv dd 36 local bus controller interface lad[0:31] e27, b20, h19, f25, a20, c19, e28, j23, a25, k22, b28, d27, d19, j22, k20, d28, d25, b25, e22, f22, f21, c25, c22, b23, f20, a23, a22, e19, a21, d21, f19, b21 i/o bv dd ? ldp[0:3] k21, c28, b26, b22 i/o bv dd ? la[27] h21 o bv dd 5, 9 la[28:31] h20, a27, d26, a28 o bv dd 5, 7, 9 lcs [0:4] j25, c20, j24, g26, a26 o bv dd lcs5 /dma_dreq2 d23 i/o bv dd 1 lcs6 /dma_dack2 g20 o bv dd 1 lcs7 /dma_ddone2 e21 o bv dd 1 lwe0 /lbs0/ lsddqm[0] g25 o bv dd 5, 9 lwe1 /lbs1/ lsddqm[1] c23 o bv dd 5, 9 lwe2 /lbs2/ lsddqm[2] j21 o bv dd 5, 9 lwe3 /lbs3/ lsddqm[3] a24 o bv dd 5, 9 lale h24 o bv dd 5, 8, 9 lbctl g27 o bv dd 5, 8, 9 lgpl0/lsda10 f23 o bv dd 5, 9 lgpl1/lsdwe g22 o bv dd 5, 9 lgpl2/loe /lsdras b27 o bv dd 5, 8, 9 lgpl3/lsdcas f24 o bv dd 5, 9 lgpl4/lgta /lupwait/lpbse h23 i/o bv dd ? lgpl5 e26 o bv dd 5, 9 lcke e24 o bv dd ? lclk[0:2] e23, d24, h22 o bv dd ? table 67. mpc8548e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 91 package description lsync_in f27 i bv dd ? lsync_out f28 o bv dd ? dma dma_dack [0:1] ad3, ae1 o ov dd 5, 9, 102 dma_dreq [0:1] ad4, ae2 i ov dd ? dma_ddone [0:1] ad2, ad1 o ov dd ? programmable interrupt controller ude ah16 i ov dd ? mcp ag19 i ov dd ? irq[0:7] ag23, af18, ae18, af20, ag18, af17, ah24, ae20 iov dd ? irq[8] af19 i ov dd ? irq[9]/dma_dreq3 af21 i ov dd 1 irq[10]/dma_dack3 ae19 i/o ov dd 1 irq[11]/dma_ddone3 ad20 i/o ov dd 1 irq_out ad18 o ov dd 2, 4 ethernet management interface ec_mdc ab9 o ov dd 5, 9 ec_mdio ac8 i/o ov dd ? gigabit reference clock ec_gtx_clk125 v11 i lv dd ? three-speed ethernet controller (gigabit ethernet 1) tsec1_rxd[7:0] r5, u1, r3, u2, v3, v1, t3, t2 i lv dd ? tsec1_txd[7:0] t10, v7, u10, u5, u4, v6, t5, t8 o lv dd 5, 9 tsec1_col r4 i lv dd ? tsec1_crs v5 i/o lv dd 20 tsec1_gtx_clk u7 o lv dd ? tsec1_rx_clk u3 i lv dd ? tsec1_rx_dv v2 i lv dd ? tsec1_rx_er t1 i lv dd ? tsec1_tx_clk t6 i lv dd ? tsec1_tx_en u9 o lv dd 30 tsec1_tx_er t7 o lv dd ? table 67. mpc8548e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 92 freescale semiconductor package description three-speed ethernet controller (gigabit ethernet 2) tsec2_rxd[7:0] p2, r2, n1, n2, p3, m2, m1, n3 i lv dd ? tsec2_txd[7:0] n9, n10, p8, n7, r9, n5, r8, n6 o lv dd 5, 9, 33 tsec2_col p1 i lv dd ? tsec2_crs r6 i/o lv dd 20 tsec2_gtx_clk p6 o lv dd tsec2_rx_clk n4 i lv dd ? tsec2_rx_dv p5 i lv dd ? tsec2_rx_er r1 i lv dd ? tsec2_tx_clk p10 i lv dd ? tsec2_tx_en p7 o lv dd 30 tsec2_tx_er r10 o lv dd 5, 9, 33 three-speed ethernet controller (gigabit ethernet 3) tsec3_txd[3:0] v8, w10, y10, w7 o tv dd 5, 9, 29 tsec3_rxd[3:0] y1, w3, w5, w4 i tv dd ? tsec3_gtx_clk w8 o tv dd ? tsec3_rx_clk w2 i tv dd ? tsec3_rx_dv w1 i tv dd ? tsec3_rx_er y2 i tv dd ? tsec3_tx_clk v10 i tv dd ? tsec3_tx_en v9 o tv dd 30 three-speed ethernet controller (gigabit ethernet 4) tsec4_txd[3:0]/tsec3_txd[7:4] ab8, y7, aa7, y8 o tv dd 1, 5, 9, 29 tsec4_rxd[3:0]/tsec3_rxd[7:4] aa1, y3, aa2, aa4 i tv dd 1 tsec4_gtx_clk aa5 o tv dd ? tsec4_rx_clk/tsec3_col y5 i tv dd 1 tsec4_rx_dv/tsec3_crs aa3 i/o tv dd 1, 31 tsec4_tx_en/tsec3_tx_er ab6 o tv dd 1, 30 duart uart_cts [0:1] ab3, ac5 i ov dd ? uart_rts [0:1] ac6, ad7 o ov dd ? uart_sin[0:1] ab5, ac7 i ov dd ? uart_sout[0:1] ab7, ad8 o ov dd ? table 67. mpc8548e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 93 package description i 2 c interface iic1_scl ag22 i/o ov dd 4, 27 iic1_sda ag21 i/o ov dd 4, 27 iic2_scl ag15 i/o ov dd 4, 27 iic2_sda ag14 i/o ov dd 4, 27 serdes sd_rx[0:7] m28, n26, p28, r26, w26, y28, aa26, ab28 i xv dd ? sd_rx [0:7] m27, n25, p27, r25, w25, y27, aa25, ab27 i xv dd ? sd_tx[0:7] m22, n20, p22, r20, u20, v22, w20, y22 o xv dd ? sd_tx [0:7] m23, n21, p23, r21, u21, v23, w21, y23 o xv dd ? sd_pll_tpd u28 o xv dd 24 sd_ref_clk t28 i xv dd 3 sd_ref_clk t27 i xv dd 3 reserved ac1, ac3 ? ? 2 reserved m26, v28 ? ? 32 reserved m25, v27 ? ? 34 reserved m20, m21, t22, t23 ? ? 38 general-purpose output gpout[24:31] k26, k25, h27, g28, h25, j26, k24, k23 o bv dd ? system control hreset ag17 i ov dd ? hreset_req ag16 o ov dd 29 sreset ag20 i ov dd ? ckstp_in aa9 i ov dd ? ckstp_out aa8 o ov dd 2, 4 debug trig_in ab2 i ov dd ? trig_out/ready/quiesce ab1 o ov dd 6, 9, 19, 29 msrcid[0:1] ae4, ag2 o ov dd 5, 6, 9 msrcid[2:4] af3, af1, af2 o ov dd 6, 19, 29 mdval ae5 o ov dd 6 clk_out ae21 o ov dd 11 table 67. mpc8548e pinout listing (continued) signal package pin number pin type power supply notes
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(ieee). this product is not endorsed or approved by the ieee. ? freescale semiconductor, inc., 2009. all rights reserved. clock rtc af16 i ov dd ? sysclk ah17 i ov dd ? jtag tck ag28 i ov dd ? tdi ah28 i ov dd 12 tdo af28 o ov dd 11 tms ah27 i ov dd 12 trst ah23 i ov dd 12 dft l1_tstclk ac25 i ov dd 25 l2_tstclk ae22 i ov dd 25 lssd_mode ah20 i ov dd 25 test_sel ah14 i ov dd 25 thermal management therm0 ag1 ? ? 14 therm1 ah1 ? ? 14 power management asleep ah18 o ov dd 9, 19, 29 power and ground signals gnd a11, b7, b24, c1, c3, c5, c12, c15, c26, d8, d11, d16, d20, d22, e1, e5, e9, e12, e15, e17, f4, f26, g12, g15, g18, g21, g24, h2, h6, h8, h28, j4, j12, j15, j17, j27, k7, k9, k11, k27, l3, l5, l12, l16, n11, n13, n15, n17, n19, p4, p9, p12, p14, p16, p18, r11, r13, r15, r17, r19, t4, t12, t14, t16, t18, u8, u11, u13, u15, u17, u19, v4, v12, v18, w6, w19, y4, y9, y11, y19, aa6, aa14, aa17, aa22, aa23, ab4, ac2, ac11, ac19, ac26, ad5, ad9, ad22, ae3, ae14, af6, af10, af13, ag8, ag27, k28, l24, l26, n24, n27, p25, r28, t24, t26, u24, v25, w28, y24, y26, aa24, aa27, ab25, ac28, l21, l23, n22, p20, r23, t21, u22, v20, w23, y21, u27 ??? ov dd v16, w11, w14, y18, aa13, aa21, ab11, ab17, ab24, ac4, ac9, ac21, ad6, ad13, ad17, ad19, ae10, ae8, ae24, af4, af12, af22, af27, ag26 power for pci and other standards (3.3 v) ov dd ? table 67. mpc8548e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 95 package description lv dd n8, r7, t9, u6 power for tsec1 and tsec2 (2.5 v, 3.3 v) lv dd ? tv dd w9, y6 power for tsec3 and tsec4 (2,5 v, 3.3 v) tv dd ? gv dd b3, b11, c7, c9, c14, c17, d4, d6, d10, d15, e2, e8, e11, e18, f5, f12, f16, g3, g7, g9, g11, h5, h12, h15, h17, j10, k3, k12, k16, k18, l6, m4, m8, m13 power for ddr1 and ddr2 dram i/o voltage (1.8 v, 2.5) gv dd ? bv dd c21, c24, c27, e20, e25, g19, g23, h26, j20 power for local bus (1.8 v, 2.5 v, 3.3 v) bv dd ? v dd m19, n12, n14, n16, n18, p11, p13, p15, p17, p19, r12, r14, r16, r18, t11, t13, t15, t17, t19, u12, u14, u16, u18, v17, v19 power for core (1.1 v) v dd ? sv dd l25, l27, m24, n28, p24, p26, r24, r27, t25, v24, v26, w24, w27, y25, aa28, ac27 core power for serdes transceivers (1.1 v) sv dd ? xv dd l20, l22, n23, p21, r22, t20, u23, v21, w22, y20 pad power for serdes transceivers (1.1 v) xv dd ? avdd_lbiu j28 power for local bus pll (1.1 v) ?26 avdd_pci1 ah21 power for pci1 pll (1.1 v) ?26 avdd_pci2 ah22 power for pci2 pll (1.1 v) ?26 avdd_core ah15 power for e500 pll (1.1 v) ?26 avdd_plat ah19 power for ccb pll (1.1 v) ?26 avdd_srds u25 power for srdspll (1.1 v) ?26 sensevdd m14 o v dd 13 sensevss m16 ? ? 13 table 67. mpc8548e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 96 freescale semiconductor package description analog signals mvref a18 i reference voltage signal for ddr mvref ? sd_imp_cal_rx l28 i 200 to gnd ? sd_imp_cal_tx ab26 i 100 to gnd ? sd_pll_tpa u26 o ? 24 notes: 1. all multiplexed signals are listed only once and do not re-occur. for example, lcs5 /dma_req2 is listed only once in the local bus controller section, and is not mentioned in the dma section even though the pin also functions as dma_req2 . 2. recommend a weak pull-up resistor (2?10 k ) be placed on this pin to ov dd . 3. a valid clock must be provided at por if tsec4_txd[2] is set = 1. 4. this pin is an open drain signal. 5. this pin is a reset configuration pin. it has a weak internal pull-up p-fet which is enabled only when the processor is in th e reset state. this pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. however, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 6. treat these pins as no connects (nc) unless using debug address functionality. 7. the value of la[28:31] during reset sets the ccb clock to sysclk pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see section 19.2, ?ccb/sysclk pll ratio.? 8. the value of lale, lgpl2, and lbctl at reset set the e500 core clock to ccb clock pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see the section 19.3, ?e500 core pll ratio.? 9. functionally, this pin is an output, but structurally it is an i/o because it either samples configuration input during reset or because it has other manufacturing test functions. this pin will therefore be described as an i/o for boundary scan. 10.this pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit pci operation. therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-b it pci device. refer to the pci specification . 11.this output is actively driven during reset rather than being three-stated during reset. 12.these jtag pins have weak internal pull-up p-fets that are always enabled. 13.these pins are connected to the v dd /gnd planes internally and may be used by the core power supply to improve tracking and regulation. 14.internal thermally sensitive resistor. 15.no connections should be made to these pins if they are not used. 16.these pins are not connected for any use. 17.pci specifications recommend that a weak pull-up resistor (2?10 k ) be placed on the higher order pins to ov dd when using 64-bit buffer mode (pins pci_ad[63:32] and pci1_c_be [7:4]). 19.if this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a sa fe state during reset. 20.this pin is only an output in fifo mode when used as rx flow control. 24.do not connect. table 67. mpc8548e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 97 package description 25.these are test signals for factory use only and must be pulled up (100 ?1 k ) to ov dd for normal machine operation. 26.independent supplies derived from board v dd . 27.recommend a pull-up resistor (~1 k ) be placed on this pin to ov dd . 29. the following pins must not be pulled down during power-on reset: tsec3_txd[3], tsec4_txd3/tsec3_txd7, hreset_req, trig_out/ready/quiesce, msrcid[2:4], asleep. 30.this pin requires an external 4.7-k pull-down resistor to prevent phy from seeing a valid transmit enable before it is actively driven. 31.this pin is only an output in etsec3 fifo mode when used as rx flow control. 32.these pins should be connected to xv dd . 33.tsec2_txd1, tsec2_tx_er are multiplexed as cfg_dram_type[0:1]. they must be valid at power-up, even before hreset assertion. 34.these pins should be pulled to ground through a 300- (10%) resistor. 35.when a pci block is disabled, either the por config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other pci device connected on the pci bus, or leave the pci n _ad pins as ? no connect? or terminated through 2?10 k pull-up resistors with the default of internal arbiter if the pci n _ad pins are not connected to any other pci device. the pci block will drive the pci n _ad pins if it is configured to be the pci arbiter?through por config pins?irrespective of whether it is disabled via the devdisr register or not. it may cause contention if there is any other pci device connected on the bus. 36.mdic0 is grounded through an 18.2- precision 1% resistor and mdic1 is connected to gv dd through an 18.2- precision 1% resistor. these pins are used for automatic calibration of the ddr ios. 38.these pins should be left floating. 39. if pci1 or pci2 is configured as pci asynchronous mode, a valid clock must be provided on pin pci1_clk or pci2_clk. otherwise the processor will not boot up. 40.these pins should be connected to gnd. 101.this pin requires an external 4.7-k resistor to gnd. 102.for rev. 2.x silicon, dma_dack [0:1] must be 0b11 during por configuration; for rev. 1.x silicon, the pin values during por configuration are don?t care. 103.if these pins are not used as gpin n (general-purpose input), they should be pulled low (to gnd) or high (to lv dd ) through 2?10 k resistors. 104.these should be pulled low to gnd through 2?10 k resistors if they are not used. 105.these should be pulled low or high to lv dd through 2?10 k resistors if they are not used. 106.for rev. 2.x silicon, dma_dack [0:1] must be 0b10 during por configuration; for rev. 1.x silicon, the pin values during por configuration are don?t care. 107.for rev. 2.x silicon, dma_dack [0:1] must be 0b01 during por configuration; for rev. 1.x silicon, the pin values during por configuration are don?t care. 108.for rev. 2.x silicon, dma_dack [0:1] must be 0b11 during por configuration; for rev. 1.x silicon, the pin values during por configuration are don?t care. 109.this is a test signal for factory use only and must be pulled down (100 ? 1 k ) to gnd for normal machine operation. 110.these pins should be pulled high to ov dd through 2?10 k resistors. 111.if these pins are not used as gpin n (general-purpose input), they should be pulled low (to gnd) or high (to ov dd ) through 2?10 k resistors. 112.this pin must not be pulled down during por configuration. 113.these should be pulled low or high to ov dd through 2?10 k resistors. table 67. mpc8548e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 98 freescale semiconductor package description table 68 provides the pin-out listing for the mpc8547e 783 fc-pbga package. note all note references in the following table use the same numbers as those for table 67 . the reader should refer to table 67 for the meanings of these notes. table 68. mpc8547e pinout listing signal package pin number pin type power supply notes pci1 (one 64-bit or one 32-bit) pci1_ad[63:32] ab14, ac15, aa15, y16, w16, ab16, ac16, aa16, ae17, aa18, w18, ac17, ad16, ae16, y17, ac18, ab18, aa19, ab19, ab21, aa20, ac20, ab20, ab22, ac22, ad21, ab23, af23, ad23, ae23, ac23, ac24 i/o ov dd 17 pci1_ad[31:0] ah6, ae7, af7, ag7, ah7, af8, ah8, ae9, ah9, ac10, ab10, ad10, ag10, aa10, ah10, aa11, ab12, ae12, ag12, ah12, ab13, aa12, ac13, ae13, y14, w13, ag13, v14, ah13, ac14, y15, ab15 i/o ov dd 17 pci1_c_be [7:4] af15, ad14, ae15, ad15 i/o ov dd 17 pci1_c_be [3:0] af9, ad11, y12, y13 i/o ov dd 17 pci1_par64 w15 i/o ov dd ? pci1_gnt [4:1] ag6, ae6, af5, ah5 o ov dd 5, 9, 35 pci1_gnt0 ag5 i/o ov dd ? pci1_irdy af11 i/o ov dd 2 pci1_par ad12 i/o ov dd ? pci1_perr ac12 i/o ov dd 2 pci1_serr v13 i/o ov dd 2, 4 pci1_stop w12 i/o ov dd 2 pci1_trdy ag11 i/o ov dd 2 pci1_req [4:1] ah2, ag4, ag3, ah4 i ov dd ? pci1_req0 ah3 i/o ov dd ? pci1_clk ah26 i ov dd 39 pci1_devsel ah11 i/o ov dd 2 pci1_frame ae11 i/o ov dd 2 pci1_idsel ag9 i ov dd ? pci1_req64 af14 i/o ov dd 2, 5,10 pci1_ack64 v15 i/o ov dd 2 reserved ae28 ? ? 2 reserved ad26 ? ? 2
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 99 package description reserved ad25 ? ? 2 reserved ae26 ? ? 2 cfg_pci1_clk ag24 i ov dd 5 reserved af25 ? ? 101 reserved ae25 ? ? 2 reserved ag25 ? ? 2 reserved ad24 ? ? 2 reserved af24 ? ? 2 reserved ad27 ? ? 2 reserved ad28, ae27, w17, af26 ? ? 2 reserved ah25 ? ? 2 ddr sdram memory interface mdq[0:63] l18, j18, k14, l13, l19, m18, l15, l14, a17, b17, a13, b12, c18, b18, b13, a12, h18, f18, j14, f15, k19, j19, h16, k15, d17, g16, k13, d14, d18, f17, f14, e14, a7, a6, d5, a4, c8, d7, b5, b4, a2, b1, d1, e4, a3, b2, d2, e3, f3, g4, j5, k5, f6, g5, j6, k4, j1, k2, m5, m3, j3, j2, l1, m6 i/o gv dd ? mecc[0:7] h13, f13, f11, c11, j13, g13, d12, m12 i/o gv dd ? mdm[0:8] m17, c16, k17, e16, b6, c4, h4, k1, e13 o gv dd ? mdqs[0:8] m15, a16, g17, g14, a5, d3, h1, l2, c13 i/o gv dd ? mdqs [0:8] l17, b16, j16, h14, c6, c2, h3, l4, d13 i/o gv dd ? ma[0:15] a8, f9, d9, b9, a9, l10, m10, h10, k10, g10, b8, e10, b10, g6, a10, l11 ogv dd ? mba[0:2] f7, j7, m11 o gv dd ? mwe e7 o gv dd ? mcas h7 o gv dd ? mras l8 o gv dd ? mcke[0:3] f10, c10, j11, h11 o gv dd 11 mcs [0:3] k8, j8, g8, f8 o gv dd ? mck[0:5] h9, b15, g2, m9, a14, f1 o gv dd ? mck [0:5] j9, a15, g1, l9, b14, f2 o gv dd ? modt[0:3] e6, k6, l7, m7 o gv dd ? mdic[0:1] a19, b19 i/o gv dd 36 table 68. mpc8547e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 100 freescale semiconductor package description local bus controller interface lad[0:31] e27, b20, h19, f25, a20, c19, e28, j23, a25, k22, b28, d27, d19, j22, k20, d28, d25, b25, e22, f22, f21, c25, c22, b23, f20, a23, a22, e19, a21, d21, f19, b21 i/o bv dd ? ldp[0:3] k21, c28, b26, b22 i/o bv dd ? la[27] h21 o bv dd 5, 9 la[28:31] h20, a27, d26, a28 o bv dd 5, 7, 9 lcs [0:4] j25, c20, j24, g26, a26 o bv dd ? lcs5 /dma_dreq2 d23 i/o bv dd 1 lcs6 /dma_dack2 g20 o bv dd 1 lcs7 /dma_ddone2 e21 o bv dd 1 lwe0 /lbs0/ lsddqm[0] g25 o bv dd 5, 9 lwe1 /lbs1/ lsddqm[1] c23 o bv dd 5, 9 lwe2 /lbs2/ lsddqm[2] j21 o bv dd 5, 9 lwe3 /lbs3/ lsddqm[3] a24 o bv dd 5, 9 lale h24 o bv dd 5, 8, 9 lbctl g27 o bv dd 5, 8, 9 lgpl0/lsda10 f23 o bv dd 5, 9 lgpl1/lsdwe g22 o bv dd 5, 9 lgpl2/loe /lsdras b27 o bv dd 5, 8, 9 lgpl3/lsdcas f24 o bv dd 5, 9 lgpl4/lgta /lupwait/lpbse h23 i/o bv dd ? lgpl5 e26 o bv dd 5, 9 lcke e24 o bv dd ? lclk[0:2] e23, d24, h22 o bv dd ? lsync_in f27 i bv dd ? lsync_out f28 o bv dd ? dma dma_dack [0:1] ad3, ae1 o ov dd 5, 9, 107 dma_dreq [0:1] ad4, ae2 i ov dd ? dma_ddone [0:1] ad2, ad1 o ov dd ? programmable interrupt controller ude ah16 i ov dd ? mcp ag19 i ov dd ? table 68. mpc8547e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 101 package description irq[0:7] ag23, af18, ae18, af20, ag18, af17, ah24, ae20 iov dd ? irq[8] af19 i ov dd ? irq[9]/dma_dreq3 af21 i ov dd 1 irq[10]/dma_dack3 ae19 i/o ov dd 1 irq[11]/dma_ddone3 ad20 i/o ov dd 1 irq_out ad18 o ov dd 2, 4 ethernet management interface ec_mdc ab9 o ov dd 5, 9 ec_mdio ac8 i/o ov dd ? gigabit reference clock ec_gtx_clk125 v11 i lv dd ? three-speed ethernet controller (gigabit ethernet 1) tsec1_rxd[7:0] r5, u1, r3, u2, v3, v1, t3, t2 i lv dd ? tsec1_txd[7:0] t10, v7, u10, u5, u4, v6, t5, t8 o lv dd 5, 9 tsec1_col r4 i lv dd ? tsec1_crs v5 i/o lv dd 20 tsec1_gtx_clk u7 o lv dd ? tsec1_rx_clk u3 i lv dd ? tsec1_rx_dv v2 i lv dd ? tsec1_rx_er t1 i lv dd ? tsec1_tx_clk t6 i lv dd ? tsec1_tx_en u9 o lv dd 30 tsec1_tx_er t7 o lv dd ? three-speed ethernet controller (gigabit ethernet 2) tsec2_rxd[7:0] p2, r2, n1, n2, p3, m2, m1, n3 i lv dd ? tsec2_txd[7:0] n9, n10, p8, n7, r9, n5, r8, n6 o lv dd 5, 9, 33 tsec2_col p1 i lv dd ? tsec2_crs r6 i/o lv dd 20 tsec2_gtx_clk p6 o lv dd ? tsec2_rx_clk n4 i lv dd ? tsec2_rx_dv p5 i lv dd ? tsec2_rx_er r1 i lv dd ? tsec2_tx_clk p10 i lv dd ? tsec2_tx_en p7 o lv dd 30 table 68. mpc8547e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 102 freescale semiconductor package description tsec2_tx_er r10 o lv dd 5, 9, 33 three-speed ethernet controller (gigabit ethernet 3) tsec3_txd[3:0] v8, w10, y10, w7 o tv dd 5, 9, 29 tsec3_rxd[3:0] y1, w3, w5, w4 i tv dd ? tsec3_gtx_clk w8 o tv dd ? tsec3_rx_clk w2 i tv dd ? tsec3_rx_dv w1 i tv dd ? tsec3_rx_er y2 i tv dd ? tsec3_tx_clk v10 i tv dd ? tsec3_tx_en v9 o tv dd 30 three-speed ethernet controller (gigabit ethernet 4) tsec4_txd[3:0]/tsec3_txd[7:4] ab8, y7, aa7, y8 o tv dd 1, 5, 9, 29 tsec4_rxd[3:0]/tsec3_rxd[7:4] aa1, y3, aa2, aa4 i tv dd 1 tsec4_gtx_clk aa5 o tv dd tsec4_rx_clk/tsec3_col y5 i tv dd 1 tsec4_rx_dv/tsec3_crs aa3 i/o tv dd 1, 31 tsec4_tx_en/tsec3_tx_er ab6 o tv dd 1, 30 duart uart_cts [0:1] ab3, ac5 i ov dd ? uart_rts [0:1] ac6, ad7 o ov dd ? uart_sin[0:1] ab5, ac7 i ov dd ? uart_sout[0:1] ab7, ad8 o ov dd ? i 2 c interface iic1_scl ag22 i/o ov dd 4, 27 iic1_sda ag21 i/o ov dd 4, 27 iic2_scl ag15 i/o ov dd 4, 27 iic2_sda ag14 i/o ov dd 4, 27 serdes sd_rx[0:3] m28, n26, p28, r26 i xv dd ? sd_rx [0:3] m27, n25, p27, r25 i xv dd ? sd_tx[0:3] m22, n20, p22, r20 o xv dd ? sd_tx [0:3] m23, n21, p23, r21 o xv dd ? reserved w26, y28, aa26, ab28 ? ? 40 reserved w25, y27, aa25, ab27 ? ? 40 table 68. mpc8547e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 103 package description reserved u20, v22, w20, y22 ? ? 15 reserved u21, v23, w21, y23 ? ? 15 sd_pll_tpd u28 o xv dd 24 sd_ref_clk t28 i xv dd ? sd_ref_clk t27 i xv dd ? reserved ac1, ac3 ? ? 2 reserved m26, v28 ? ? 32 reserved m25, v27 ? ? 34 reserved m20, m21, t22, t23 ? ? 38 general-purpose output gpout[24:31] k26, k25, h27, g28, h25, j26, k24, k23 o bv dd ? system control hreset ag17 i ov dd ? hreset_req ag16 o ov dd 29 sreset ag20 i ov dd ? ckstp_in aa9 i ov dd ? ckstp_out aa8 o ov dd 2, 4 debug trig_in ab2 i ov dd ? trig_out/ready/quiesce ab1 o ov dd 6, 9, 19, 29 msrcid[0:1] ae4, ag2 o ov dd 5, 6, 9 msrcid[2:4] af3, af1, af2 o ov dd 6, 19, 29 mdval ae5 o ov dd 6 clk_out ae21 o ov dd 11 clock rtc af16 i ov dd ? sysclk ah17 i ov dd ? jtag tck ag28 i ov dd ? tdi ah28 i ov dd 12 tdo af28 o ov dd 11 tms ah27 i ov dd 12 trst ah23 i ov dd 12 table 68. mpc8547e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 104 freescale semiconductor package description dft l1_tstclk ac25 i ov dd 25 l2_tstclk ae22 i ov dd 25 lssd_mode ah20 i ov dd 25 test_sel ah14 i ov dd 25 thermal management therm0 ag1 ? ? 14 therm1 ah1 ? ? 14 power management asleep ah18 o ov dd 9, 19, 29 power and ground signals gnd a11, b7, b24, c1, c3, c5, c12, c15, c26, d8, d11, d16, d20, d22, e1, e5, e9, e12, e15, e17, f4, f26, g12, g15, g18, g21, g24, h2, h6, h8, h28, j4, j12, j15, j17, j27, k7, k9, k11, k27, l3, l5, l12, l16, n11, n13, n15, n17, n19, p4, p9, p12, p14, p16, p18, r11, r13, r15, r17, r19, t4, t12, t14, t16, t18, u8, u11, u13, u15, u17, u19, v4, v12, v18, w6, w19, y4, y9, y11, y19, aa6, aa14, aa17, aa22, aa23, ab4, ac2, ac11, ac19, ac26, ad5, ad9, ad22, ae3, ae14, af6, af10, af13, ag8, ag27, k28, l24, l26, n24, n27, p25, r28, t24, t26, u24, v25, w28, y24, y26, aa24, aa27, ab25, ac28, l21, l23, n22, p20, r23, t21, u22, v20, w23, y21, u27 ??? ov dd v16, w11, w14, y18, aa13, aa21, ab11, ab17, ab24, ac4, ac9, ac21, ad6, ad13, ad17, ad19, ae10, ae8, ae24, af4, af12, af22, af27, ag26 power for pci and other standards (3.3 v) ov dd ? lv dd n8, r7, t9, u6 power for tsec1 and tsec2 (2.5 v, 3.3 v) lv dd ? tv dd w9, y6 power for tsec3 and tsec4 (2,5 v, 3.3 v) tv dd ? gv dd b3, b11, c7, c9, c14, c17, d4, d6, d10, d15, e2, e8, e11, e18, f5, f12, f16, g3, g7, g9, g11, h5, h12, h15, h17, j10, k3, k12, k16, k18, l6, m4, m8, m13 power for ddr1 and ddr2 dram i/o voltage (1.8 v, 2.5 v) gv dd ? table 68. mpc8547e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 105 package description bv dd c21, c24, c27, e20, e25, g19, g23, h26, j20 power for local bus (1.8 v, 2.5 v, 3.3 v) bv dd ? v dd m19, n12, n14, n16, n18, p11, p13, p15, p17, p19, r12, r14, r16, r18, t11, t13, t15, t17, t19, u12, u14, u16, u18, v17, v19 power for core (1.1 v) v dd ? sv dd l25, l27, m24, n28, p24, p26, r24, r27, t25, v24, v26, w24, w27, y25, aa28, ac27 core power for serdes transceivers (1.1 v) sv dd ? xv dd l20, l22, n23, p21, r22, t20, u23, v21, w22, y20 pad power for serdes transceivers (1.1 v) xv dd ? avdd_lbiu j28 power for local bus pll (1.1 v) ?26 avdd_pci1 ah21 power for pci1 pll (1.1 v) ?26 avdd_pci2 ah22 power for pci2 pll (1.1 v) ?26 avdd_core ah15 power for e500 pll (1.1 v) ?26 avdd_plat ah19 power for ccb pll (1.1 v) ?26 avdd_srds u25 power for srdspll (1.1 v) ?26 sensevdd m14 o v dd 13 sensevss m16 ? ? 13 analog signals mvref a18 i reference voltage signal for ddr mvref ? sd_imp_cal_rx l28 i 200 to gnd ? sd_imp_cal_tx ab26 i 100 to gnd ? sd_pll_tpa u26 o ? 24 note: all note references in this table use the same numbers as those for ta b l e 6 7 . the reader should refer to ta ble 6 7 for the meanings of these notes. table 68. mpc8547e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 106 freescale semiconductor package description table 69 provides the pin-out listing for the mpc8545e 783 fc-pbga package. note all note references in the following table use the same numbers as those for table 67 . the reader should refer to table 67 for the meanings of these notes. table 69. mpc8545e pinout listing signal package pin number pin type power supply notes pci1 and pci2 (one 64-bit or two 32-bit) pci1_ad[63:32]/pci2_ad[31:0] ab14, ac15, aa15, y16, w16, ab16, ac16, aa16, ae17, aa18, w18, ac17, ad16, ae16, y17, ac18, ab18, aa19, ab19, ab21, aa20, ac20, ab20, ab22, ac22, ad21, ab23, af23, ad23, ae23, ac23, ac24 i/o ov dd 17 pci1_ad[31:0] ah6, ae7, af7, ag7, ah7, af8, ah8, ae9, ah9, ac10, ab10, ad10, ag10, aa10, ah10, aa11, ab12, ae12, ag12, ah12, ab13, aa12, ac13, ae13, y14, w13, ag13, v14, ah13, ac14, y15, ab15 i/o ov dd 17 pci1_c_be [7:4]/pci2_c_be [3:0] af15, ad14, ae15, ad15 i/o ov dd 17 pci1_c_be [3:0] af9, ad11, y12, y13 i/o ov dd 17 pci1_par64/pci2_par w15 i/o ov dd ? pci1_gnt [4:1] ag6, ae6, af5, ah5 o ov dd 5, 9, 35 pci1_gnt0 ag5 i/o ov dd ? pci1_irdy af11 i/o ov dd 2 pci1_par ad12 i/o ov dd ? pci1_perr ac12 i/o ov dd 2 pci1_serr v13 i/o ov dd 2, 4 pci1_stop w12 i/o ov dd 2 pci1_trdy ag11 i/o ov dd 2 pci1_req [4:1] ah2, ag4, ag3, ah4 i ov dd ? pci1_req0 ah3 i/o ov dd ? pci1_clk ah26 i ov dd 39 pci1_devsel ah11 i/o ov dd 2 pci1_frame ae11 i/o ov dd 2 pci1_idsel ag9 i ov dd ? pci1_req64 /pci2_frame af14 i/o ov dd 2, 5, 10 pci1_ack64 /pci2_devsel v15 i/o ov dd 2 pci2_clk ae28 i ov dd 39 pci2_irdy ad26 i/o ov dd 2
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 107 package description pci2_perr ad25 i/o ov dd 2 pci2_gnt [4:1] ae26, ag24, af25, ae25 o ov dd 5, 9, 35 pci2_gnt0 ag25 i/o ov dd ? pci2_serr ad24 i/o ov dd 2,4 pci2_stop af24 i/o ov dd 2 pci2_trdy ad27 i/o ov dd 2 pci2_req [4:1] ad28, ae27, w17, af26 i ov dd ? pci2_req0 ah25 i/o ov dd ? ddr sdram memory interface mdq[0:63] l18, j18, k14, l13, l19, m18, l15, l14, a17, b17, a13, b12, c18, b18, b13, a12, h18, f18, j14, f15, k19, j19, h16, k15, d17, g16, k13, d14, d18, f17, f14, e14, a7, a6, d5, a4, c8, d7, b5, b4, a2, b1, d1, e4, a3, b2, d2, e3, f3, g4, j5, k5, f6, g5, j6, k4, j1, k2, m5, m3, j3, j2, l1, m6 i/o gv dd ? mecc[0:7] h13, f13, f11, c11, j13, g13, d12, m12 i/o gv dd ? mdm[0:8] m17, c16, k17, e16, b6, c4, h4, k1, e13 o gv dd ? mdqs[0:8] m15, a16, g17, g14, a5, d3, h1, l2, c13 i/o gv dd ? mdqs [0:8] l17, b16, j16, h14, c6, c2, h3, l4, d13 i/o gv dd ? ma[0:15] a8, f9, d9, b9, a9, l10, m10, h10, k10, g10, b8, e10, b10, g6, a10, l11 ogv dd ? mba[0:2] f7, j7, m11 o gv dd ? mwe e7 o gv dd ? mcas h7 o gv dd ? mras l8 o gv dd ? mcke[0:3] f10, c10, j11, h11 o gv dd 11 mcs [0:3] k8, j8, g8, f8 o gv dd ? mck[0:5] h9, b15, g2, m9, a14, f1 o gv dd ? mck [0:5] j9, a15, g1, l9, b14, f2 o gv dd ? modt[0:3] e6, k6, l7, m7 o gv dd ? mdic[0:1] a19, b19 i/o gv dd 36 local bus controller interface lad[0:31] e27, b20, h19, f25, a20, c19, e28, j23, a25, k22, b28, d27, d19, j22, k20, d28, d25, b25, e22, f22, f21, c25, c22, b23, f20, a23, a22, e19, a21, d21, f19, b21 i/o bv dd ? ldp[0:3] k21, c28, b26, b22 i/o bv dd ? table 69. mpc8545e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 108 freescale semiconductor package description la[27] h21 o bv dd 5, 9 la[28:31] h20, a27, d26, a28 o bv dd 5, 7, 9 lcs [0:4] j25, c20, j24, g26, a26 o bv dd ? lcs5 /dma_dreq2 d23 i/o bv dd 1 lcs6 /dma_dack2 g20 o bv dd 1 lcs7 /dma_ddone2 e21 o bv dd 1 lwe0 /lbs0/ lsddqm[0] g25 o bv dd 5, 9 lwe1 /lbs1/ lsddqm[1] c23 o bv dd 5, 9 lwe2 /lbs2/ lsddqm[2] j21 o bv dd 5, 9 lwe3 /lbs3/ lsddqm[3] a24 o bv dd 5, 9 lale h24 o bv dd 5, 8, 9 lbctl g27 o bv dd 5, 8, 9 lgpl0/lsda10 f23 o bv dd 5, 9 lgpl1/lsdwe g22 o bv dd 5, 9 lgpl2/loe /lsdras b27 o bv dd 5, 8, 9 lgpl3/lsdcas f24 o bv dd 5, 9 lgpl4/lgta /lupwait/lpbse h23 i/o bv dd ? lgpl5 e26 o bv dd 5, 9 lcke e24 o bv dd ? lclk[0:2] e23, d24, h22 o bv dd ? lsync_in f27 i bv dd ? lsync_out f28 o bv dd ? dma dma_dack [0:1] ad3, ae1 o ov dd 5, 9, 106 dma_dreq [0:1] ad4, ae2 i ov dd ? dma_ddone [0:1] ad2, ad1 o ov dd ? programmable interrupt controller ude ah16 i ov dd ? mcp ag19 i ov dd ? irq[0:7] ag23, af18, ae18, af20, ag18, af17, ah24, ae20 iov dd ? irq[8] af19 i ov dd ? irq[9]/dma_dreq3 af21 i ov dd 1 irq[10]/dma_dack3 ae19 i/o ov dd 1 table 69. mpc8545e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 109 package description irq[11]/dma_ddone3 ad20 i/o ov dd 1 irq_out ad18 o ov dd 2, 4 ethernet management interface ec_mdc ab9 o ov dd 5, 9 ec_mdio ac8 i/o ov dd ? gigabit reference clock ec_gtx_clk125 v11 i lv dd ? three-speed ethernet controller (gigabit ethernet 1) tsec1_rxd[7:0] r5, u1, r3, u2, v3, v1, t3, t2 i lv dd ? tsec1_txd[7:0] t10, v7, u10, u5, u4, v6, t5, t8 o lv dd 5, 9 tsec1_col r4 i lv dd ? tsec1_crs v5 i/o lv dd 20 tsec1_gtx_clk u7 o lv dd ? tsec1_rx_clk u3 i lv dd ? tsec1_rx_dv v2 i lv dd ? tsec1_rx_er t1 i lv dd ? tsec1_tx_clk t6 i lv dd ? tsec1_tx_en u9 o lv dd 30 tsec1_tx_er t7 o lv dd ? gpin[0:7] p2, r2, n1, n2, p3, m2, m1, n3 i lv dd 103 gpout[0:5] n9, n10, p8, n7, r9, n5 o lv dd ? cfg_dram_type0/gpout6 r8 o lv dd 5, 9 gpout7 n6 o lv dd ? reserved p1 ? ? 104 reserved r6 ? ? 104 reserved p6 ? ? 15 reserved n4 ? ? 105 fifo1_rxc2 p5 i lv dd 104 reserved r1 ? ? 104 reserved p10 ? ? 105 fifo1_txc2 p7 o lv dd 15 cfg_dram_type1 r10 i lv dd 5 three-speed ethernet controller (gigabit ethernet 3) tsec3_txd[3:0] v8, w10, y10, w7 o tv dd 5, 9, 29 table 69. mpc8545e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 110 freescale semiconductor package description tsec3_rxd[3:0] y1, w3, w5, w4 i tv dd ? tsec3_gtx_clk w8 o tv dd ? tsec3_rx_clk w2 i tv dd ? tsec3_rx_dv w1 i tv dd ? tsec3_rx_er y2 i tv dd ? tsec3_tx_clk v10 i tv dd ? tsec3_tx_en v9 o tv dd 30 tsec3_txd[7:4] ab8, y7, aa7, y8 o tv dd 5, 9, 29 tsec3_rxd[7:4] aa1, y3, aa2, aa4 i tv dd ? reserved aa5 ? ? 15 tsec3_col y5 i tv dd ? tsec3_crs aa3 i/o tv dd 31 tsec3_tx_er ab6 o tv dd ? duart uart_cts [0:1] ab3, ac5 i ov dd ? uart_rts [0:1] ac6, ad7 o ov dd ? uart_sin[0:1] ab5, ac7 i ov dd ? uart_sout[0:1] ab7, ad8 o ov dd ? i 2 c interface iic1_scl ag22 i/o ov dd 4, 27 iic1_sda ag21 i/o ov dd 4, 27 iic2_scl ag15 i/o ov dd 4, 27 iic2_sda ag14 i/o ov dd 4, 27 serdes sd_rx[0:3] m28, n26, p28, r26 i xv dd ? sd_rx [0:3] m27, n25, p27, r25 i xv dd ? sd_tx[0:3] m22, n20, p22, r20 o xv dd ? sd_tx [0:3] m23, n21, p23, r21 o xv dd ? reserved w26, y28, aa26, ab28 ? ? 40 reserved w25, y27, aa25, ab27 ? ? 40 reserved u20, v22, w20, y22 ? ? 15 reserved u21, v23, w21, y23 ? ? 15 sd_pll_tpd u28 o xv dd 24 sd_ref_clk t28 i xv dd ? table 69. mpc8545e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 111 package description sd_ref_clk t27 i xv dd ? reserved ac1, ac3 ? ? 2 reserved m26, v28 ? ? 32 reserved m25, v27 ? ? 34 reserved m20, m21, t22, t23 ? ? 38 general-purpose output gpout[24:31] k26, k25, h27, g28, h25, j26, k24, k23 o bv dd ? system control hreset ag17 i ov dd ? hreset_req ag16 o ov dd 29 sreset ag20 i ov dd ? ckstp_in aa9 i ov dd ? ckstp_out aa8 o ov dd 2, 4 debug trig_in ab2 i ov dd ? trig_out/ready/quiesce ab1 o ov dd 6, 9, 19, 29 msrcid[0:1] ae4, ag2 o ov dd 5, 6, 9 msrcid[2:4] af3, af1, af2 o ov dd 6, 19, 29 mdval ae5 o ov dd 6 clk_out ae21 o ov dd 11 clock rtc af16 i ov dd ? sysclk ah17 i ov dd ? jtag tck ag28 i ov dd ? tdi ah28 i ov dd 12 tdo af28 o ov dd 11 tms ah27 i ov dd 12 trst ah23 i ov dd 12 dft l1_tstclk ac25 i ov dd 25 l2_tstclk ae22 i ov dd 25 lssd_mode ah20 i ov dd 25 table 69. mpc8545e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 112 freescale semiconductor package description test_sel ah14 i ov dd 25 thermal management therm0 ag1 ? ? 14 therm1 ah1 ? ? 14 power management asleep ah18 o ov dd 9, 19, 29 power and ground signals gnd a11, b7, b24, c1, c3, c5, c12, c15, c26, d8, d11, d16, d20, d22, e1, e5, e9, e12, e15, e17, f4, f26, g12, g15, g18, g21, g24, h2, h6, h8, h28, j4, j12, j15, j17, j27, k7, k9, k11, k27, l3, l5, l12, l16, n11, n13, n15, n17, n19, p4, p9, p12, p14, p16, p18, r11, r13, r15, r17, r19, t4, t12, t14, t16, t18, u8, u11, u13, u15, u17, u19, v4, v12, v18, w6, w19, y4, y9, y11, y19, aa6, aa14, aa17, aa22, aa23, ab4, ac2, ac11, ac19, ac26, ad5, ad9, ad22, ae3, ae14, af6, af10, af13, ag8, ag27, k28, l24, l26, n24, n27, p25, r28, t24, t26, u24, v25, w28, y24, y26, aa24, aa27, ab25, ac28, l21, l23, n22, p20, r23, t21, u22, v20, w23, y21, u27 ??? ov dd v16, w11, w14, y18, aa13, aa21, ab11, ab17, ab24, ac4, ac9, ac21, ad6, ad13, ad17, ad19, ae10, ae8, ae24, af4, af12, af22, af27, ag26 power for pci and other standards (3.3 v) ov dd ? lv dd n8, r7, t9, u6 power for tsec1 and tsec2 (2.5 v, 3.3 v) lv dd ? tv dd w9, y6 power for tsec3 and tsec4 (2,5 v, 3.3 v) tv dd ? gv dd b3, b11, c7, c9, c14, c17, d4, d6, d10, d15, e2, e8, e11, e18, f5, f12, f16, g3, g7, g9, g11, h5, h12, h15, h17, j10, k3, k12, k16, k18, l6, m4, m8, m13 power for ddr1 and ddr2 dram i/o voltage (1.8 v, 2.5 v) gv dd ? bv dd c21, c24, c27, e20, e25, g19, g23, h26, j20 power for local bus (1.8 v, 2.5 v, 3.3 v) bv dd ? table 69. mpc8545e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 113 package description v dd m19, n12, n14, n16, n18, p11, p13, p15, p17, p19, r12, r14, r16, r18, t11, t13, t15, t17, t19, u12, u14, u16, u18, v17, v19 power for core (1.1 v) v dd ? sv dd l25, l27, m24, n28, p24, p26, r24, r27, t25, v24, v26, w24, w27, y25, aa28, ac27 core power for serdes transceivers (1.1 v) sv dd ? xv dd l20, l22, n23, p21, r22, t20, u23, v21, w22, y20 pad power for serdes transceivers (1.1 v) xv dd ? avdd_lbiu j28 power for local bus pll (1.1 v) ?26 avdd_pci1 ah21 power for pci1 pll (1.1 v) ?26 avdd_pci2 ah22 power for pci2 pll (1.1 v) ?26 avdd_core ah15 power for e500 pll (1.1 v) ?26 avdd_plat ah19 power for ccb pll (1.1 v) ?26 avdd_srds u25 power for srdspll (1.1 v) ?26 sensevdd m14 o v dd 13 sensevss m16 ? ? 13 analog signals mvref a18 i reference voltage signal for ddr mvref ? sd_imp_cal_rx l28 i 200 to gnd ? sd_imp_cal_tx ab26 i 100 to gnd ? sd_pll_tpa u26 o ? 24 note: all note references in this table use the same numbers as those for ta b l e 6 7 . the reader should refer to ta ble 6 7 for the meanings of these notes. table 69. mpc8545e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 114 freescale semiconductor package description table 70 provides the pin-out listing for the mpc8543e 783 fc-pbga package. note all note references in the following table use the same numbers as those for table 67 . the reader should refer to table 67 for the meanings of these notes. table 70. mpc8543e pinout listing signal package pin number pin type power supply notes pci1 (one 32-bit) reserved ab14, ac15, aa15, y16, w16, ab16, ac16, aa16, ae17, aa18, w18, ac17, ad16, ae16, y17, ac18, ??110 gpout[8:15] ab18, aa19, ab19, ab21, aa20, ac20, ab20, ab22 oov dd ? gpin[8:15] ac22, ad21, ab23, af23, ad23, ae23, ac23, ac24 iov dd 111 pci1_ad[31:0] ah6, ae7, af7, ag7, ah7, af8, ah8, ae9, ah9, ac10, ab10, ad10, ag10, aa10, ah10, aa11, ab12, ae12, ag12, ah12, ab13, aa12, ac13, ae13, y14, w13, ag13, v14, ah13, ac14, y15, ab15 i/o ov dd 17 reserved af15, ad14, ae15, ad15 ? ? 110 pci1_c_be [3:0] af9, ad11, y12, y13 i/o ov dd 17 reserved w15 ? ? 110 pci1_gnt [4:1] ag6, ae6, af5, ah5 o ov dd 5, 9, 35 pci1_gnt0 ag5 i/o ov dd ? pci1_irdy af11 i/o ov dd 2 pci1_par ad12 i/o ov dd ? pci1_perr ac12 i/o ov dd 2 pci1_serr v13 i/o ov dd 2, 4 pci1_stop w12 i/o ov dd 2 pci1_trdy ag11 i/o ov dd 2 pci1_req [4:1] ah2, ag4, ag3, ah4 i ov dd ? pci1_req0 ah3 i/o ov dd ? pci1_clk ah26 i ov dd 39 pci1_devsel ah11 i/o ov dd 2 pci1_frame ae11 i/o ov dd 2 pci1_idsel ag9 i ov dd ? cfg_pci1_width af14 i/o ov dd 112 reserved v15 ? ? 110
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 115 package description reserved ae28 ? ? 2 reserved ad26 ? ? 110 reserved ad25 ? ? 110 reserved ae26 ? ? 110 cfg_pci1_clk ag24 i ov dd 5 reserved af25 ? ? 101 reserved ae25 ? ? 110 reserved ag25 ? ? 110 reserved ad24 ? ? 110 reserved af24 ? ? 110 reserved ad27 ? ? 110 reserved ad28, ae27, w17, af26 ? ? 110 reserved ah25 ? ? 110 ddr sdram memory interface mdq[0:63] l18, j18, k14, l13, l19, m18, l15, l14, a17, b17, a13, b12, c18, b18, b13, a12, h18, f18, j14, f15, k19, j19, h16, k15, d17, g16, k13, d14, d18, f17, f14, e14, a7, a6, d5, a4, c8, d7, b5, b4, a2, b1, d1, e4, a3, b2, d2, e3, f3, g4, j5, k5, f6, g5, j6, k4, j1, k2, m5, m3, j3, j2, l1, m6 i/o gv dd ? mecc[0:7] h13, f13, f11, c11, j13, g13, d12, m12 i/o gv dd ? mdm[0:8] m17, c16, k17, e16, b6, c4, h4, k1, e13 o gv dd ? mdqs[0:8] m15, a16, g17, g14, a5, d3, h1, l2, c13 i/o gv dd ? mdqs [0:8] l17, b16, j16, h14, c6, c2, h3, l4, d13 i/o gv dd ? ma[0:15] a8, f9, d9, b9, a9, l10, m10, h10, k10, g10, b8, e10, b10, g6, a10, l11 ogv dd ? mba[0:2] f7, j7, m11 o gv dd ? mwe e7 o gv dd ? mcas h7 o gv dd ? mras l8 o gv dd ? mcke[0:3] f10, c10, j11, h11 o gv dd 11 mcs [0:3] k8, j8, g8, f8 o gv dd ? mck[0:5] h9, b15, g2, m9, a14, f1 o gv dd ? mck [0:5] j9, a15, g1, l9, b14, f2 o gv dd ? modt[0:3] e6, k6, l7, m7 o gv dd ? mdic[0:1] a19, b19 i/o gv dd 36 table 70. mpc8543e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 116 freescale semiconductor package description local bus controller interface lad[0:31] e27, b20, h19, f25, a20, c19, e28, j23, a25, k22, b28, d27, d19, j22, k20, d28, d25, b25, e22, f22, f21, c25, c22, b23, f20, a23, a22, e19, a21, d21, f19, b21 i/o bv dd ? ldp[0:3] k21, c28, b26, b22 i/o bv dd ? la[27] h21 o bv dd 5, 9 la[28:31] h20, a27, d26, a28 o bv dd 5, 7, 9 lcs [0:4] j25, c20, j24, g26, a26 o bv dd ? lcs5 /dma_dreq2 d23 i/o bv dd 1 lcs6 /dma_dack2 g20 o bv dd 1 lcs7 /dma_ddone2 e21 o bv dd 1 lwe0 /lbs0/ lsddqm[0] g25 o bv dd 5, 9 lwe1 /lbs1/ lsddqm[1] c23 o bv dd 5, 9 lwe2 /lbs2/ lsddqm[2] j21 o bv dd 5, 9 lwe3 /lbs3/ lsddqm[3] a24 o bv dd 5, 9 lale h24 o bv dd 5, 8, 9 lbctl g27 o bv dd 5, 8, 9 lgpl0/lsda10 f23 o bv dd 5, 9 lgpl1/lsdwe g22 o bv dd 5, 9 lgpl2/loe /lsdras b27 o bv dd 5, 8, 9 lgpl3/lsdcas f24 o bv dd 5, 9 lgpl4/lgta /lupwait/lpbse h23 i/o bv dd ? lgpl5 e26 o bv dd 5, 9 lcke e24 o bv dd ? lclk[0:2] e23, d24, h22 o bv dd ? lsync_in f27 i bv dd ? lsync_out f28 o bv dd ? dma dma_dack [0:1] ad3, ae1 o ov dd 5, 9, 108 dma_dreq [0:1] ad4, ae2 i ov dd ? dma_ddone [0:1] ad2, ad1 o ov dd ? programmable interrupt controller ude ah16 i ov dd ? mcp ag19 i ov dd ? table 70. mpc8543e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 117 package description irq[0:7] ag23, af18, ae18, af20, ag18, af17, ah24, ae20 iov dd ? irq[8] af19 i ov dd ? irq[9]/dma_dreq3 af21 i ov dd 1 irq[10]/dma_dack3 ae19 i/o ov dd 1 irq[11]/dma_ddone3 ad20 i/o ov dd 1 irq_out ad18 o ov dd 2, 4 ethernet management interface ec_mdc ab9 o ov dd 5, 9 ec_mdio ac8 i/o ov dd ? gigabit reference clock ec_gtx_clk125 v11 i lv dd ? three-speed ethernet controller (gigabit ethernet 1) tsec1_rxd[7:0] r5, u1, r3, u2, v3, v1, t3, t2 i lv dd ? tsec1_txd[7:0] t10, v7, u10, u5, u4, v6, t5, t8 o lv dd 5, 9 tsec1_col r4 i lv dd ? tsec1_crs v5 i/o lv dd 20 tsec1_gtx_clk u7 o lv dd ? tsec1_rx_clk u3 i lv dd ? tsec1_rx_dv v2 i lv dd ? tsec1_rx_er t1 i lv dd ? tsec1_tx_clk t6 i lv dd ? tsec1_tx_en u9 o lv dd 30 tsec1_tx_er t7 o lv dd ? gpin[0:7] p2, r2, n1, n2, p3, m2, m1, n3 i lv dd 103 gpout[0:5] n9, n10, p8, n7, r9, n5 o lv dd ? cfg_dram_type0/gpout6 r8 o lv dd 5, 9 gpout7 n6 o lv dd ? reserved p1 ? ? 104 reserved r6 ? ? 104 reserved p6 ? ? 15 reserved n4 ? ? 105 fifo1_rxc2 p5 i lv dd 104 reserved r1 ? ? 104 table 70. mpc8543e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 118 freescale semiconductor package description reserved p10 ? ? 105 fifo1_txc2 p7 o lv dd 15 cfg_dram_type1 r10 o lv dd 5, 9 three-speed ethernet controller (gigabit ethernet 3) tsec3_txd[3:0] v8, w10, y10, w7 o tv dd 5, 9, 29 tsec3_rxd[3:0] y1, w3, w5, w4 i tv dd ? tsec3_gtx_clk w8 o tv dd ? tsec3_rx_clk w2 i tv dd ? tsec3_rx_dv w1 i tv dd ? tsec3_rx_er y2 i tv dd ? tsec3_tx_clk v10 i tv dd ? tsec3_tx_en v9 o tv dd 30 tsec3_txd[7:4] ab8, y7, aa7, y8 o tv dd 5, 9, 29 tsec3_rxd[7:4] aa1, y3, aa2, aa4 i tv dd ? reserved aa5 ? ? 15 tsec3_col y5 i tv dd ? tsec3_crs aa3 i/o tv dd 31 tsec3_tx_er ab6 o tv dd ? duart uart_cts [0:1] ab3, ac5 i ov dd ? uart_rts [0:1] ac6, ad7 o ov dd ? uart_sin[0:1] ab5, ac7 i ov dd ? uart_sout[0:1] ab7, ad8 o ov dd ? i 2 c interface iic1_scl ag22 i/o ov dd 4, 27 iic1_sda ag21 i/o ov dd 4, 27 iic2_scl ag15 i/o ov dd 4, 27 iic2_sda ag14 i/o ov dd 4, 27 serdes sd_rx[0:7] m28, n26, p28, r26, w26, y28, aa26, ab28 i xv dd ? sd_rx [0:7] m27, n25, p27, r25, w25, y27, aa25, ab27 i xv dd ? sd_tx[0:7] m22, n20, p22, r20, u20, v22, w20, y22 o xv dd ? sd_tx [0:7] m23, n21, p23, r21, u21, v23, w21, y23 o xv dd ? sd_pll_tpd u28 o xv dd 24 table 70. mpc8543e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 119 package description sd_ref_clk t28 i xv dd ? sd_ref_clk t27 i xv dd ? reserved ac1, ac3 ? ? 2 reserved m26, v28 ? ? 32 reserved m25, v27 ? ? 34 reserved m20, m21, t22, t23 ? ? 38 general-purpose output gpout[24:31] k26, k25, h27, g28, h25, j26, k24, k23 o bv dd ? system control hreset ag17 i ov dd ? hreset_req ag16 o ov dd 29 sreset ag20 i ov dd ? ckstp_in aa9 i ov dd ? ckstp_out aa8 o ov dd 2, 4 debug trig_in ab2 i ov dd ? trig_out/ready/quiesce ab1 o ov dd 6, 9, 19, 29 msrcid[0:1] ae4, ag2 o ov dd 5, 6, 9 msrcid[2:4] af3, af1, af2 o ov dd 6, 19, 29 mdval ae5 o ov dd 6 clk_out ae21 o ov dd 11 clock rtc af16 i ov dd ? sysclk ah17 i ov dd ? jtag tck ag28 i ov dd ? tdi ah28 i ov dd 12 tdo af28 o ov dd 11 tms ah27 i ov dd 12 trst ah23 i ov dd 12 dft l1_tstclk ac25 i ov dd 25 l2_tstclk ae22 i ov dd 25 table 70. mpc8543e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 120 freescale semiconductor package description lssd_mode ah20 i ov dd 25 test_sel ah14 i ov dd 109 thermal management therm0 ag1 ? ? 14 therm1 ah1 ? ? 14 power management asleep ah18 o ov dd 9, 19, 29 power and ground signals gnd a11, b7, b24, c1, c3, c5, c12, c15, c26, d8, d11, d16, d20, d22, e1, e5, e9, e12, e15, e17, f4, f26, g12, g15, g18, g21, g24, h2, h6, h8, h28, j4, j12, j15, j17, j27, k7, k9, k11, k27, l3, l5, l12, l16, n11, n13, n15, n17, n19, p4, p9, p12, p14, p16, p18, r11, r13, r15, r17, r19, t4, t12, t14, t16, t18, u8, u11, u13, u15, u17, u19, v4, v12, v18, w6, w19, y4, y9, y11, y19, aa6, aa14, aa17, aa22, aa23, ab4, ac2, ac11, ac19, ac26, ad5, ad9, ad22, ae3, ae14, af6, af10, af13, ag8, ag27, k28, l24, l26, n24, n27, p25, r28, t24, t26, u24, v25, w28, y24, y26, aa24, aa27, ab25, ac28, l21, l23, n22, p20, r23, t21, u22, v20, w23, y21, u27 ??? ov dd v16, w11, w14, y18, aa13, aa21, ab11, ab17, ab24, ac4, ac9, ac21, ad6, ad13, ad17, ad19, ae10, ae8, ae24, af4, af12, af22, af27, ag26 power for pci and other standards (3.3 v) ov dd ? lv dd n8, r7, t9, u6 power for tsec1 and tsec2 (2.5 v, 3.3 v) lv dd ? tv dd w9, y6 power for tsec3 and tsec4 (2,5 v, 3.3 v) tv dd ? gv dd b3, b11, c7, c9, c14, c17, d4, d6, d10, d15, e2, e8, e11, e18, f5, f12, f16, g3, g7, g9, g11, h5, h12, h15, h17, j10, k3, k12, k16, k18, l6, m4, m8, m13 power for ddr1 and ddr2 dram i/o voltage (1.8 v,2.5 v) gv dd ? table 70. mpc8543e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 121 package description bv dd c21, c24, c27, e20, e25, g19, g23, h26, j20 power for local bus (1.8 v, 2.5 v, 3.3 v) bv dd ? v dd m19, n12, n14, n16, n18, p11, p13, p15, p17, p19, r12, r14, r16, r18, t11, t13, t15, t17, t19, u12, u14, u16, u18, v17, v19 power for core (1.1 v) v dd ? sv dd l25, l27, m24, n28, p24, p26, r24, r27, t25, v24, v26, w24, w27, y25, aa28, ac27 core power for serdes transceivers (1.1 v) sv dd ? xv dd l20, l22, n23, p21, r22, t20, u23, v21, w22, y20 pad power for serdes transceivers (1.1 v) xv dd ? avdd_lbiu j28 power for local bus pll (1.1 v) ?26 avdd_pci1 ah21 power for pci1 pll (1.1 v) ?26 avdd_pci2 ah22 power for pci2 pll (1.1 v) ?26 avdd_core ah15 power for e500 pll (1.1 v) ?26 avdd_plat ah19 power for ccb pll (1.1 v) ?26 avdd_srds u25 power for srdspll (1.1 v) ?26 sensevdd m14 o v dd 13 sensevss m16 ? ? 13 analog signals mvref a18 i reference voltage signal for ddr mvref ? sd_imp_cal_rx l28 i 200 (1%) to gnd ? table 70. mpc8543e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 122 freescale semiconductor clocking 19 clocking this section describes the pll configuration of the mpc8548e. note that the platform clock is identical to the core complex bus (ccb) clock. 19.1 clock ranges table 71 through table 73 provide the clocking specifications for the processor cores and table 74 , through table 76 provide the clocking specifications for the memory bus. sd_imp_cal_tx ab26 i 100 (1%) to gnd ? sd_pll_tpa u26 o avdd_srds 24 note: all note references in this table use the same numbers as those for table 67 . the reader should refer to ta b l e 6 7 for the meanings of these notes. table 71. processor core clocking specifications (mpc8548e and mpc8547e) characteristic maximum processor core frequency unit notes 1000 mhz 1200 mhz 1333 mhz min max min max min max e500 core processor frequency 800 1000 800 1200 800 1333 mhz 1, 2 notes : 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2.)the minimum e500 core frequency is based on the minimum platform frequency of 333 mhz. table 72. processor core clocking specifications (mpc8545e) characteristic maximum processor core frequency unit notes 800 mhz 1000 mhz 1200 mhz min max min max min max e500 core processor frequency 800 800 800 1000 800 1200 mhz 1, 2 notes : 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2.)the minimum e500 core frequency is based on the minimum platform frequency of 333 mhz. table 70. mpc8543e pinout listing (continued) signal package pin number pin type power supply notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 123 clocking table 73. processor core clocking specifications (mpc8543e) characteristic maximum processor core frequency unit notes 800 mhz 1000 mhz min max min max e500 core processor frequency 800 800 800 1000 mhz 1, 2 notes : 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2.)the minimum e500 core frequency is based on the minimum platform frequency of 333 mhz. table 74. memory bus clocking specifications (mpc8548e and mpc8547e) characteristic maximum processor core frequency unit notes 1000, 1200, 1333 mhz min max memory bus clock speed 166 266 mhz 1, 2 notes: 1. caution: the ccb clock to sysclk ratio and e500 core to ccb clock ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2. the memory bus speed is half of the ddr/ddr2 data rate, hence, half of the platform clock frequency. table 75. memory bus clocking specifications (mpc8545e) characteristic maximum processor core frequency unit notes 800, 1000, 1200 mhz min max memory bus clock speed 166 200 mhz 1, 2 notes: 1. caution: the ccb clock to sysclk ratio and e500 core to ccb clock ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2. the memory bus speed is half of the ddr/ddr2 data rate, hence, half of the platform clock frequency.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 124 freescale semiconductor clocking 19.2 ccb/sysclk pll ratio the ccb clock is the clock that drives the e500 core complex bus (ccb), and is also called the platform clock. the frequency of the ccb is set using the following reset signals, as shown in table 77 : ? sysclk input signal ? binary value on la[28:31] at power up note that there is no default for this pll ratio; these signals must be pulled to the desired values. also note that the ddr data rate is the determining factor in selecting the ccb bus frequency, since the ccb frequency must equal the ddr data rate. for specifications on the pci_clk, refer to the pci 2.2 specification . table 76. memory bus clocking specifications (mpc8543e) characteristic maximum processor core frequency unit notes 800, 1000 mhz min max memory bus clock speed 166 200 mhz 1, 2 notes: 1. caution: the ccb clock to sysclk ratio and e500 core to ccb clock ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2. the memory bus speed is half of the ddr/ddr2 data rate, hence, half of the platform clock frequency. table 77. ccb clock ratio binary value of la[28:31] signals ccb:sysclk ratio binary value of la[28:31] signals ccb:sysclk ratio 0000 16:1 1000 8:1 0001 reserved 1001 9:1 0010 2:1 1010 10:1 0011 3:1 1011 reserved 0100 4:1 1100 12:1 0101 5:1 1101 20:1 0110 6:1 1110 reserved 0111 reserved 1111 reserved
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 125 clocking 19.3 e500 core pll ratio table 78 describes the clock ratio between the e500 core complex bus (ccb) and the e500 core clock. this ratio is determined by the binary value of lbctl, lale, and lgpl2 at power up, as shown in table 78 . 19.4 frequency options 19.4.1 sysclk to platform frequency options table 79 shows the expected frequency values for the platform frequency when using a ccb clock to sysclk ratio in comparison to the memory bus clock speed. table 78. e500 core to ccb clock ratio binary value of lbctl, lale, lgpl2 signals e500 core:ccb clock ratio binary value of lbctl, lale, lgpl2 signals e500 core:ccb clock ratio 000 4:1 100 2:1 001 9:2 101 5:2 010 reserved 110 3:1 011 3:2 111 7:2 table 79. frequency options of sysclk with respect to memory bus speeds ccb to sysclk ratio sysclk (mhz) 16.66 25 33.33 41.66 66.66 83 100 111 133.33 platform/ccb frequency (mhz) 2 3 333 400 4 333 400 445 533 5 333 415 500 6 400 500 8 333 533 9 375 10 333 417 12 400 500 16 400 533 20 333 500 note: due to errata gen 13 the max sys clk frequency should not exceed 100 mhz if the core clk frequency is below 1200 mhz.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 126 freescale semiconductor thermal 20 thermal this section describes the thermal specifications of the mpc8548. 20.1 thermal for version 2.0 silicon hicte fc-cbga with full lid this section describes the thermal specifications for the hicte fc-cbga package for revision 2.0 silicon. table 80 shows the package thermal characteristics. 20.2 thermal for version 2.1.1 and 2.1.2 silicon fc-pbga with full lid this section describes the thermal specifications for the fc-pbga package for revision 2.1.1 silicon. table 81 shows the package thermal characteristics. table 80. package thermal characteristics for hicte fc-cbga characteristic jedec board symbol value unit notes die junction-to-ambient (natural convection) single-layer board (1s) r ja 17 c/w 1, 2 die junction-to-ambient (natural convection) four-layer board (2s2p) r ja 12 c/w 1, 2 die junction-to-ambient (200 ft/min) single-layer board (1s) r ja 11 c/w 1, 2 die junction-to-ambient (200 ft/min) four-layer board (2s2p) r ja 8c/w1, 2 die junction-to-board n/a r jb 3c/w3 die junction-to-case n/a r jc 0.8 c/w 4 notes: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-6 with the board (jesd51-7) horizontal. 3. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). the cold plate temperature is used for the case temperature, measured value includes the thermal resistance of the interface layer. table 81. package thermal characteristics for fc-pbga characteristic jedec board symbol value unit notes die junction-to-ambient (natural convection) single-layer board (1s) r ja 18 c/w 1, 2 die junction-to-ambient (natural convection) four-layer board (2s2p) r ja 13 c/w 1, 2 die junction-to-ambient (200 ft/min) single-layer board (1s) r ja 13 c/w 1, 2 die junction-to-ambient (200 ft/min) four-layer board (2s2p) r ja 9c/w1, 2 die junction-to-board n/a r jb 5c/w3
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 127 system design information 20.3 heat sink solution every system application has different conditions that the thermal management solution must solve. as such, providing a recommended heat sink has not been found to be very useful. when a heat sink is chosen, give special consideration to the mounting technique. mounting the heat sink to the printed-circuit board is the recommended procedure using a maximum of 10 lbs force (45 newtons) perpendicular to the package and board. clipping the heat sink to the package is not recommended. 21 system design information this section provides electrical design recommendations for successful application of the mpc8548e. 21.1 system clocking this device includes five plls, as follows: 1. the platform pll generates the platform clock from the externally supplied sysclk input. the frequency ratio between the platform and sysclk is selected using the platform pll ratio configuration bits as described in section 19.2, ?ccb/sysclk pll ratio.? 2. the e500 core pll generates the core clock as a slave to the platform clock. the frequency ratio between the e500 core clock and the platform clock is selected using the e500 pll ratio configuration bits as described in section 19.3, ?e500 core pll ratio.? 3. the pci pll generates the clocking for the pci bus. 4. the local bus pll generates the clock for the local bus. 5. there is a pll for the serdes block. die junction-to-case n/a r jc 0.8 c/w 4 notes: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-6 with the board (jesd51-7) horizontal. 3. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). the cold plate temperature is used for the case temperature, measured value includes the thermal resistance of the interface layer. table 81. package thermal characteristics for fc-pbga (continued) characteristic jedec board symbol value unit notes
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 128 freescale semiconductor system design information 21.2 power supply design 21.2.1 pll power supply filtering each of the plls listed above is provided w ith power through independent power supply pins (av dd _plat, av dd _core, av dd _pci, av dd _lbiu, and av dd _srds, respectively). the av dd level should always be equivalent to v dd , and preferably these voltages will be derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide independent filter circuits pe r pll power supply as illustrated in figure 56 , one to each of the av dd pins. by providing independent filters to each pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as cl ose as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd pin, which is on the periphery of the footprint, without the inductance of vias. figure 56 through figure 58 shows the pll power supply filter circuits. figure 56. pll power supply filter circuit with plat pins figure 57. pll power supply filter circuit with core pins figure 58. pll power supply filter circuit with pci/lbiu pins v dd av dd _plat 2.2 f 2.2 f gnd low esl surface mount capacitors 150 v dd av dd _core 2.2 f 2.2 f gnd low esl surface mount capacitors 180 v dd av dd _pci/av dd _lbiu 2.2 f 2.2 f gnd low esl surface mount capacitors 10
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 129 system design information the av dd _srds signal provides power for the analog portions of the serdes pll. to ensure stability of the internal clock, the power supplied to the pll is filtered using a circuit similar to the one shown in following figure. for maximum effectiveness, the filter circuit is placed as closely as possible to the av dd _srds ball to ensure it filters out as much noise as possible. the ground connection should be near the av dd _srds ball. the 0.003-f capacitor is closest to the ball, followed by the two 2.2 f capacitors, and finally the 1 resistor to the board supply plane. the capacitors are connected from av dd _srds to the ground plane. use ceramic chip capacitors with the highest possible self-resonant frequency. all traces should be kept short, wide and direct. figure 59. serdes pll power supply filter note the following: ?av dd _srds should be a filtered version of sv dd . ? signals on the serdes interface are fed from the xv dd power plane. 21.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the device can generate transient power surges and high frequency noise in its power suppl y, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc8548e system, and the device itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , tv dd , bv dd , ov dd , gv dd , and lv dd pin of the device. these decoupling capacitors should receive their power from separate v dd , tv dd , bv dd , ov dd , gv dd , lv dd , and gnd power planes in the pcb, utilizing short low impedance traces to minimize inductance. capacitors must be placed dire ctly under the device using a standard escape pattern as much as possible. if some caps are to be placed surrounding the part it should be routed with large trace to minimize the inductance. these capacitors should have a value of 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , tv dd , bv dd , ov dd , gv dd , and lv dd , planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should ha ve a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). however, customers should work directly with their power regulator vendor for best values, types and quantity of bulk capacitors. 2.2 f 1 0.003 f 1.0 av dd _srds note: 1. an 0805 sized capacitor is recommended for system initial bring-up. sv dd 2.2 f 1 gnd
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 130 freescale semiconductor system design information 21.4 serdes block power supply decoupling recommendations the serdes block requires a clean, tightly regulated source of power (sv dd and xv dd ) to ensure low jitter on transmit and reliable recovery of data in the receiver. an appropriate decoupling scheme is outlined below. only surface mount technology (smt) capacitors shoul d be used to minimize inductance. connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. ? first, the board should have at least 10 10-nf smt ceramic chip capacitors as close as possible to the supply balls of the device. where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connecti ons. where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. ? second, there should be a 1-f ceramic chip capacitor from each serdes supply (sv dd and xv dd ) to the board ground plane on each side of th e device. this should be done for all serdes supplies. ? third, between the device and any serdes voltage regulator there should be a 10-f, low equivalent series resistance (esr) smt tantalum chip capacitor and a 100-f, low esr smt tantalum chip capacitor. this shoul d be done for all serdes supplies. 21.5 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. all unused active low inputs should be tied to v dd , tv dd , bv dd , ov dd , gv dd , and lv dd , as required. all unused active high inputs should be conne cted to gnd. all nc (no-connect) signals must remain unconnected. power and ground connecti ons must be made to all external v dd , tv dd , bv dd , ov dd , gv dd , lv dd , and gnd pins of the device. 21.6 pull-up and pull-down resistor requirements the mpc8548e requires weak pull-up resistors (2?10 k is recommended) on open drain type pins including i 2 c pins and pic (interrupt) pins. correct operation of the jtag interface requires configuration of a group of system control pins as demonstrated in figure 62 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. the following pins must not be pulled down during power-on reset: tsec3_txd[3], hreset_req , trig_out/ready/quiesce , msrcid[2:4], asleep. the dma_dack [0:1], and test_sel/ test_sel pins must be set to a proper state during por configuration. refer to the pinlist table of the individual device for more details refer to the pci 2.2 specification for all pull ups required for pci.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 131 system design information 21.7 output buffer dc impedance the mpc8548e drivers are characterized over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 60 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 60. driver impedance measurement table 82 summarizes the signal impedance targets. the driver impedances are targeted at minimum v dd , nominal ov dd , 105 c. 21.8 configuration pin muxing the mpc8548e provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal function. most of these sampled configuration pins are equipped with an on-chip gated resi stor of approximately 20 k . this value should permit the 4.7-k resistor to pull table 82. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci ddr dram symbol unit r n 43 target 25 target 20 target z 0 w r p 43 target 25 target 20 target z 0 w note: nominal supply voltages. see ta b l e 1 , t j = 105 c. ov dd ognd pad data sw1 sw2 r n r p
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 132 freescale semiconductor system design information the configuration pin to a valid logic low level. the pull-up resistor is enabled only during hreset (and for platform/system clocks after hreset deassertion to ensure capture of the reset value). when the input receiver is disabled the pull-up is also, thus allowi ng functional operation of the pin as an output with minimal signal quality or delay disruption. the default va lue for all configuration bits treated this way has been encoded such that a high voltage level puts the de vice into the default state and external resistors are needed only when non-default settings are required by the user. careful board layout with stubless connections to th ese pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. the platform pll ratio and e500 pll ratio configura tion pins are not equipped with these default pull-up devices. 21.9 jtag configuration signals correct operation of the jtag interface requires configuration of a group of system control pins as demonstrated in figure 62 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but it is provided on all processors built on power architecture technology. the device requires trst to be asserted during power-on reset flow to ensure that the jtag boundary logic does not interfere with normal chip operation. while the tap controller can be forced to the reset state using only the tck and tms signals, generally systems assert trst during the power-on reset flow. simply tying trst to hreset is not practical because the jtag interface is also used for accessing the common on-chip processor (cop), which implements the debug interface to the chip. the cop function of these processors allow a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system ha s independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 62 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. the cop interface has a standard header, shown in figure 61 , for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. the cop header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and othe r standard debugger features. an inexpensive option can be to leave the cop header unpopulated until needed. there is no standardized way to number the cop head er; so emulator vendors have issued many different pin numbering schemes. some cop headers are numbere d top-to-bottom then left-to-right, while others
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 133 system design information use left-to-right then top-to-bottom. still others numbe r the pins counter-clockwise from pin 1 (as with an ic). regardless of the numbering scheme, the signal placement recommended in figure 61 is common to all known emulators. 21.9.1 termination of unused signals if the jtag interface and cop header will not be used, freescale recommends the following connections: ?trst should be tied to hreset through a 0 k isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during the power-on reset flow. freescale recommends that the cop header be designed into the system as shown in figure 62 . if this is not possible, the isolation resistor will allow future access to trst in case a jtag interface may need to be wired onto the system in future debug situations. ? no pull-up/pull-down is required for tdi, tms, tdo, or tck. figure 61. cop connector physical pinout 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin 1 2 cop_tdo cop_tdi cop_run/stop nc cop_trst cop_vdd_sense cop_chkstp_in nc nc gnd cop_tck cop_tms cop_sreset cop_hreset cop_chkstp_out
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 134 freescale semiconductor system design information figure 62. jtag interface connection hreset from target board sources cop_hreset 13 cop_sreset sreset nc 11 cop_vdd_sense 2 6 5 15 10 10 k 10 k cop_chkstp_in ckstp_in 8 cop_tms cop_tdo cop_tdi cop_tck tms tdo tdi 9 1 3 4 cop_trst 7 16 2 10 12 (if any) cop header 14 3 notes: 3. the key location (pin 14) is not physically present on the cop header. 10 k trst 1 10 k 10 k 10 k ckstp_out cop_chkstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin cop connector physical pinout 1 2 nc sreset 2. populate this with a 10 ? resistor for short-circuit/current-limiting protection. nc ov dd 10 k hreset 1 in order to fully control the processor as shown here. 4. although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional gnd pin for 1. the cop port and target board should be able to independently assert hreset and trst to the processor improved signal integrity. tck 4 5 5. this switch is included as a precaution for bsdl testing. the switch should be closed to position a during bsdl testing to avoid accidentally asserting the trst line. if bsdl testing is not being performed, this switch should be 10 k 6 6. asserting sreset causes a machine check interrupt to the e500 core. a b closed to position b.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 135 system design information 21.10 guidelines for high-speed interface termination 21.10.1 serdes interface entirely unused if the high-speed serdes interface is not used at all, the unused pin should be terminated as described in this section. the following pins must be left unconnected (float): ?sd_tx[7:0] ?sd_tx [7:0] ? reserved pins t22, t23, m20, m21 the following pins must be connected to gnd: ?sd_rx[7:0] ?sd_rx [7:0] ?sd_ref_clk ? sd_ref_clk note it is recommended to power down the unused lane through srdscr1[0:7] register (offset = 0xe_0f08) (this prevents the oscillations and holds the receiver output in a fixed state.) that maps to serdes lane 0 to lane 7 accordingly. pins v28 and m26 must be tied to xv dd . pins v27 and m25 must be tied to gnd through a 300- resistor. in rev 2.0 silicon, por configuration pin cfg_srds_en on tsec4_txd[2]/tsec3_txd[6] can be used to power down serdes block. 21.10.2 serdes interface partly unused if only part of the high-speed serdes interface pins are used, the remaining high-speed serial i/o pins should be terminated as described in this section. the following pins must be left unconnected (float) if not used: ?sd_tx[7:0] ?sd_tx [7:0] ? reserved pins: t22, t23, m20, m21 the following pins must be connected to gnd if not used: ?sd_rx[7:0] ?sd_rx [7:0] ?sd_ref_clk ? sd_ref_clk
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 136 freescale semiconductor ordering information note it is recommended to power down the unused lane through srdscr1[0:7] register (offset = 0xe_0f08) (this prevents the oscillations and holds the receiver output in a fixed state) that maps to serdes lane 0 to lane 7 accordingly. pins v28 and m26 must be tied to xv dd . pins v27 and m25 must be tied to gnd through a 300- resistor. 21.11 guideline for pci interface termination pci termination if pci 1 or pci 2 is not used at all. option 1 if pci arbiter is enabled during por: ? all ad pins will be driven to the stable states after por. therefore, all ads pins can be floating. ? all pci control pins can be grouped together and tied to ov dd through a single 10-k resistor. ? it is optional to disable pci block through devdisr register after por reset. option 2 if pci arbiter is disabled during por: ? all ad pins will be in the input state. therefore, all ads pins need to be grouped together and tied to ov dd through a single (or multiple) 10-k resistor(s). ? all pci control pins can be grouped together and tied to ov dd through a single 10-k resistor. ? it is optional to disable pci block through devdisr register after por reset. 21.12 guideline for lbiu termination if the lbiu parity pins are not used, the following is the termination recommendation: ? for ldp[0:3]?tie them to ground or the power supply rail via a 4.7-k resistor. ? for lpbse?tie it to the power supply rail via a 4.7-k resistor (pull-up resistor). 22 ordering information ordering information for the parts fully covered by this specification document is provided in section 22.1, ?part numbers fully addressed by this document.? 22.1 part numbers fully addressed by this document table 83 provides the freescale part numbering nomenclat ure for the mpc8548e. note that the individual part numbers correspond to a maximum processor core frequency. for available fr equencies, contact your local freescale sales office. in addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify sp ecial application conditions. each part number also contains a revision code which refers to the die mask revision number.
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 137 ordering information table 83. part numbering nomenclature mpc nnnnn t pp ff c r product code part identifier temperature package 1, 2, 3 processor frequency 4 core frequency silicon version mpc 8548e blank = 0 to 105 c c = ?40 to 105 c hx = cbga vu = pb-free cbga px = pbga vt = pb-free pbga av = 1500 3 au = 1333 at = 1200 aq = 1000 j = 533 h = 500 5 g = 400 blank = ver. 2.0 (svr = 0x80390020) a = ver. 2.1.1 b = ver. 2.1.2 (svr = 0x80390021) 8548 blank = ver. 2.0 (svr = 0x80310020) a = ver. 2.1.1 b = ver. 2.1.2 (svr = 0x80310021) 8547e au = 1333 at = 1200 aq = 1000 j = 533 g = 400 blank = ver. 2.0 (svr = 0x80390120) a = ver. 2.1.1 b = ver. 2.1.2 (svr = 0x80390121) 8547 blank = ver. 2.0 (svr = 0x80390120) a = ver. 2.1.1 b = ver. 2.1.2 (svr = 0x80310121) 8545e at = 1200 aq = 1000 an = 800 g = 400 blank = ver. 2.0 (svr = 0x80390220) a = ver. 2.1.1 b = ver. 2.1.2 (svr = 0x80390221) 8545 blank = ver. 2.0 (svr = 0x80310220) a = ver. 2.1.1 b = ver. 2.1.2 (svr = 0x80310221) 8543e aq = 1000 an = 800 blank = ver. 2.0 (svr = 0x803a0020) a = ver. 2.1.1 b = ver. 2.1.2 (svr = 0x803a0021) 8543 blank = ver. 2.0 (svr = 0x80320020) a = ver. 2.1.1 b = ver. 2.1.2 (svr = 0x80320021) notes: 1. see section 18, ?package description,? for more information on available package types. 2. the hicte fc-cbga package is available on only version 2.0 of the device. 3. the fc-pbga package is available on only version 2.1.1 and 2.1.2 of the device. 4. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies. 5. this speed available only for silicon version 2.1.1.and 2.1.2
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 138 freescale semiconductor ordering information 22.2 part marking parts are marked as the example shown in figure 63 . figure 63. part marking for cbga and pbga device mmmmm ccccc notes : ccccc is the country of assembly. this space is left blank if parts are assembled in the united states. twlyyww is final test traceability code. mmmmm is 5 digit mask number. mpc8548xxxxxx twlyww ywwlaz ywwlaz is assembly traceability code. (f)
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 139 document revision history 23 document revision history table 84 provides a revision history for the mpc8548e hardware specification. table 84. document revision history revision date substantive change(s) 5 10/2009 ? in table 27 , ?gmii receive ac timing specifications,? changed duty cycle specification from 40/60 to 35/75 for rx_clk duty cycle. ? updated tmdkhdx in table 37 , ?mii management ac timing specifications.? ? added a reference to revision 2.1.2. ? updated table 55, ? mii management ac timing specifications.? ? added section 5.1, ?power-on ramp rate .? 4 04/2009 ? in tab le 1 , ?absolute maximum ratings 1 ,? and in ta b l e 2 , ?recommended operating conditions,? moved text, ?mii management voltage? from lv dd /tv dd to ov dd , added ?ethernet management? to ovdd row of input voltage section. ?in ta b l e 5 , ?sysclk ac timing specifications,? added notes 7 and 8 to sysclk frequency and cycle time. ?in tab le 3 6 , ?mii management dc electrical characteristics,? changed all instances of lv dd /ov dd to ov dd . ? modified section 15, ?high-speed serial interfaces (hssi) ,? to reflect that there is only one serdes. ? modified ddr clk rate min from 133 to 166 mhz. ? modified note in ta ble 7 1 , ?processor core clocking specifications (mpc8548e and mpc8547e), ?.? ?in table 52, ?differential transmitter (tx) output specifications,? modified equations in comments column, and changed all instances of ?lo? to ?l0.? in addition, added note 8. ?in table 53, ?differential receiver (rx) input specifications,? modified equations in comments column, and in note 3, changed ?trx-eye-median-to-max-jitter,? to ?t rx-eye-median-to-max-jitter .? ? modified ta b l e 7 9 , ?frequency options of sysclk with respect to memory bus speeds.? ? added a note on section 4.1, ?system clock timing ,? to limit the sysclk to 100 mhz if the core frequency is less than 1200 mhz ?in table 67, ?mpc8548e pinout listing ta b l e 6 8 , ?mpc8547e pinout listing table 69, ?mpc8545e pinout listing table 70, ?mpc8543e pinout listing,? added note 5 to la[28:31]. ? added note to table 79 , ?frequency options of sysclk with respect to memory bus speeds.?
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 140 freescale semiconductor document revision history 3 01/2009 ? [ section 4.6, ?platform frequency requirements for pci-express and serial rapidio.? changed minimum frequency equation to be 527 mhz for pci x8. ?in tab le 5 , added note 7. ? section 4.5, ?platform to fifo restrictions.? changed platform clock frequency to 4.2. ? section 8.1, ?enhanced three-speed ethernet controller (etsec) (10/100/1gb mbps)?gmii/mii/tbi/rgmii/rtbi/rmii electrical characteristics.? added mii after gmii and add ?or 2.5 v? after 3.3 v. ?in tab le 2 3 , modified table title to include gmii, mii, rmii, and tbi. ?in tab le 2 4 and ta b l e 2 5 , changed clock period minimum to 5.3. ?in tab le 2 5 , added a note. ?in tab le 2 6 , ta b l e 2 7 , ta b l e 2 8 , ta b l e 2 9 , and tab le 3 0 , removed subtitle from table title. ?in tab le 3 0 and figure 15 , changed all instances of pma to tsec n . ?in section 8.2.5, ?tbi single-clock mode ac specifications.? replaced first paragraph. ?in tab le 3 4 , ta b l e 3 5 , figure 18 , and figure 20 , changed all instances of ref_clk to tsec n _tx_clk. ?in tab le 3 6 , changed all instances of ov dd to lv dd /tv dd . ?in tab le 3 7 , ?mii management ac timing specifications,? changed mdc minimum clock pulse width high from 32 to 48 ns. ? added new section, section 15, ?high-speed serial interfaces (hssi).? ? section 16.1, ?dc requirements for pci express sd_ref_clk and sd_ref_clk.? added new paragraph. ? section 17.1, ?dc requirements for serial rapidio sd_ref_clk and sd_ref_clk.? added new paragraph. ? added information to figure 63 , both in figure and in note. ? section 21.3, ?decoupling recommendations.? modified the recommendation. ? table 83, ?part numbering nomenclature.? in silicon version column added ver. 2.1.2. 2 04/2008 ? removed 1:1 support on table 78, ?e500 core to ccb clock ratio .? ? removed mdm from table 18, ?ddr sdram input ac timing specifications .? mdm is an output. ? figure 56, ?pll power supply filter circuit with plat pins ? (avdd_plat). ? figure 57, ?pll power supply filter circuit with core pins ? (avdd_core). ?split figure 58, ?pll power supply filter circuit with pci/lbiu pins ,? (formerly called just ?pll power supply filter circuit?) into three figures: the original (now specific for avdd_pci/avdd_lbiu) and two new ones. table 84. document revision history (continued) revision date substantive change(s)
mpc8548e powerquicc? iii integrated processor hardware specifications, rev. 5 freescale semiconductor 141 document revision history 1 10/2007 ? adjusted maximum sysclk frequency down in table 5, ?sysclk ac timing specifications ? per device erratum gen-13. ? clarified notes to table 6, ?ec_gtx_clk125 ac timing specifications .? ? added section 4.4, ?pci/pci-x reference clock timing .? ? clarified descriptions and added pci/pci-x to table 9, ?pll lock times .? ? removed support for 266 and 200 mbps data rates per device erratum gen-13 in section 6, ?ddr and ddr2 sdram .? ? clarified note 4 of table 19, ?ddr sdram output ac timing specifications .? ? clarified the reference clock used in section 7.2, ?duart ac electrical specifications .? ? corrected v ih (min) in table 22, ?gmii, mii, rmii, and tbi dc electrical characteristics .? ? corrected v il (max) in table 23, ?gmii, mii, rmii, tbi, rgmii, rtbi, and fifo dc electrical characteristics .? ? removed dc parameters from ta b l e 2 4 , tab le 2 5 , ta b l e 2 6 , ta b l e 2 7 , table 28 , ta ble 2 9 , ta b l e 3 2 , ta b l e 3 4 , and ta b l e 3 5 . ? corrected v ih (min) in table 36, ?mii management dc electrical characteristics .? ? corrected t mdc (min) in table 37, ?mii management ac timing specifications .? ? updated parameter descriptions for t lbivkh1 , t lbivkh2 , t lbixkh1 , and t lbixkh2 in table 40, ?local bus timing parameters (bv dd = 3.3 v)?pll enabled ? and table 40, ?local bus timing parameters (bv dd = 2.5 v)?pll enabled .? ? updated parameter descriptions for t lbivkh1 , t lbivkl2 , t lbixkh1 , and t lbixkl2 in table 42, ?local bus timing parameters?pll bypassed .? note that t lbivkl2 and t lbixkl2 were previously labeled t lbivkh2 and t lbixkh2 . ? added lupwait signal to figure 23, ?local bus signals (pll enabled) ? and figure 24, ?local bus signals (pll bypass mode) .? ? added lgta signal to figure 25 , figure 26 , figure 27 and figure 28 . ? corrected lupwait assertion in figure 26 and figure 28 . ? clarified the pci reference clock in section 14.2, ?pci/pci-x ac electrical specifications ? ? added section 17.1, ?package parameters .? ? added pbga thermal information in section 20.2, ?thermal for version 2.1.1 and 2.1.2 silicon fc-pbga with full lid .? ? updated.? ? updated table 83, ?part numbering nomenclature .? 0 07/2007 ? initial release table 84. document revision history (continued) revision date substantive change(s)
document number: mpc8548eec rev. 5 10/2009 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale are trademarks or registered trademarks of freescale semiconductor, inc. in the u.s. and other countries. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ieee 802.3, 802.2, 802.1, and 1149.1 are registered trademarks of the institute of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. ? freescale semiconductor, inc., 2009. all rights reserved.

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